Differential space-time block coding apparatus using eight or less transmit antennas

• US 20050135499A1
• Filed: 12/23/2004
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Nam, Seung-Hoon, Tarokh, Vahid, Kim, Yung-Soo, Hwang, Chan-Soo, Chung, Jae-Hak
• Granted Patent: US 7,864,876 B2
• Time in Patent Office: Days
• US Class Current: 375/267
• CPC Class Codes: H04L 1/0643 block codes

Abstract

A differential STBC transmitting/receiving apparatus in a multiple antenna system using eight or less transmit antennas is provided. In the differential STBC transmitting apparatus, a symbol mapper receives binary data and generates a number of symbols from the binary data, each symbol having a number of bits. A space-time block encoder generates an STBC by encoding the symbols. A differential processor differentially encodes the STBC through feedback and delay. A distribution matrix processor substitutes the differentially coded STBC into a distribution matrix preset according to the number of transmit antennas, and outputs the differential STBC code of the distribution matrix to the transmit antennas.

Claims

1. An apparatus for transmitting a space-time block code (STBC) in a multiple antenna system, comprising:

a symbol mapper for receiving binary data and generating a number of symbols from the binary data, each symbol having a number of bits;

a space-time block encoder for generating an STBC by encoding the symbols;

a differential processor for differentially encoding the STBC through feedback and delay; and

a distribution matrix processor for substituting the differentially encoded STBC into a distribution matrix, and outputting the differential STBC code of the distribution matrix to the transmit antennas.

2. The apparatus of claim 1, wherein the differential processor comprises:

a multiplier for multiplying an STBC (S_v+1) by a delayed output signal (B_v) and outputting the differentially coded STBC (B_v+1); and

a delay for delaying a previous output signal (B_v) of the multiplier and outputting the delayed signal (B_v) to the multiplier.

3. An apparatus for receiving a space-time block code (STBC) in a multiple antenna system, comprising:

a vector generator for receiving an STBC from a transmitter and generating a vector (R_v+1) from the STBC;

a differential deprocessor for simultaneously outputting the vector (R_v+1) and a delayed previous vector (R_v);

a coherent space-time block decoder for estimating symbols using the vector (R_v+1) and the delayed previous vector (R_v); and

a symbol demapper for demapping the estimated symbols to binary data.

4. The apparatus of claim 3, wherein the differential deprocessor comprises:

a transmission path for passing the vector (R_v+1) received from the vector generator; and

a delay for delaying the previous vector (R_v) received from the vector generator so that the previous vector (R_v) and the vector (R_v+1) can be output simultaneously.