Semiconductor on insulator vertical transistor fabrication and doping process

• US 20050136604A1
• Filed: 12/01/2004
• Published: 06/23/2005
• Est. Priority Date: 08/10/2000
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ramaswamy, Kartik, Hanawa, Hiroji, Collins, Kenneth S., Nguyen, Andrew, Al-Bayati, Amir, Gallo, Biagio
• Granted Patent: US 7,294,563 B2
• Time in Patent Office: Days
• US Class Current: 438/301
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.

Claims

1. A process for fabricating a vertical transistor on a semiconductor-on-insulator wafer consisting of an underlying substrate, an intermediate insulator layer and a top crystalline semiconductor active layer, said process comprising:

sculpting from said active layer a 3-dimensional source-channel-drain structure having horizontal and vertical surfaces and comprising a channel with a source and drain at either end of the channel;

forming a thin gate oxide layer over a section of the channel;

forming a 3-dimensional gate structure over said thin gate oxide layer;

while supporting the wafer in a plasma immersion ion implantation reactor chamber, introducing into the chamber a dopant-containing process gas and applying RF plasma source power into the chamber to generate from said process gas a plasma; and

applying RF plasma bias power or voltage to the wafer to draw ions from the plasma toward the wafer across a plasma sheath at a sufficient energy to implant the ions in the source-drain-channel structure.

2. The process of claim 1 further comprising:

setting said bias power or voltage at a sufficiently high level to attain a threshold conformality of ion implant dose on the horizontal and vertical surfaces of the source-channel-drain structure.

3. The process of claim 2 wherein:

the step of forming a 3-dimensional gate structure comprises forming a polycrystalline semiconductor gate; and

a threshold conformality of ion implant dose is attained on the horizontal and vertical surfaces of the 3-dimensional gate structure.

4. The process of claim 1 wherein the level of said RF plasma bias power or voltage is sufficient to promote scattering of the ions in the plasma sheath of the plasma by enhancing the thickness of the plasma sheath.

5. The process of claim 1 wherein the level of said RF plasma bias power is sufficient to establish a wafer bias voltage on the order of a sub-kilovolt to several kilovolts.

6. The process of claim 1 further comprising maintaining the RF plasma source power at a sufficiently low level to enhance the conformality of the ion implant dose.

7. The process of claim 6 wherein the level of the RF plasma source power is on the order of hundreds of Watts.

8. The process of claim 1 further comprising maintaining a sufficiently high pressure over the wafer to enhance the conformality of the ion implant dose.

9. The process of claim 8 wherein the pressure over the wafer is on the order of about 80 milliTorr.

10. The process of claim 1 further comprising enhancing the conformality of the ion implant dose by supplementing the dopant containing process gas with a second gas species having a collision cross-section that is greater than the collision cross section of the dopant containing process gas.

11. The process of claim 10 wherein the supplementing step comprises supplying into the chamber said second gas species at a gas flow rate that is between about 5% and 95% of the gas flow rate of the dopant containing gas.

12. The process of claim 10 wherein said second gas species comprises Xenon, Kr, Ar, Ne, He or H2.

13. The process of claim 1 further comprising:

maintaining the RF plasma source power at a sufficiently low level to enhance the conformality of the ion implant dose; and

maintaining a sufficiently high pressure over the wafer to enhance the conformality of the ion implant dose.

14. The process of claim 13 wherein:

the level of said RF plasma bias power is sufficient to establish a wafer bias voltage on the order of sub-kV to kilovolts;

the level of the RF plasma source power is on the order of hundreds of Watts; and

the pressure over the wafer is on the order of about 80 milliTorr.

15. The process of claim 14 further comprising:

supplementing the dopant containing process gas with a second gas species having a collision cross-section that is greater than the collision cross section of the dopant containing process gas.

16. The process of claim 15 wherein:

said second gas species comprises xenon, Kr, Ar, Ne, He or H2.

17. The process of claim 1 wherein said dopant containing process gas comprises one of B2H6, BF3, PH3, PF3, AsH3, AsF5, PF5, AsF3.

18. The process of claim 1 further comprising performing a post-implant anneal process on the wafer.

19. The process of claim 1 wherein the threshold conformality is on the order of magnitude of about 10%.

20. The process of claim 1 wherein:

said reactor comprises an external reentrant conduit having a pair of openings into said chamber defining a toroidal path extending across a processing zone overlying said workpiece; and

the step of generating a plasma comprises generating an RF oscillating plasma current along said toroidal path.

44. The process of claim 19 comprising maintaining a bias voltage on the wafer corresponding to an ion implantation depth profile that peaks at or near the surfaces of the vertical transistor.

45. The process of claim 44 wherein the ion implantation depth profile peak is within a fraction of a micron of each surface of the vertical transistor.

49. The process of claim 1 further comprising maintaining said wafer at a sufficiently high temperature to prevent accumulation of ion bombardment damage or amorphization of the source-channel-drain structure.

50. The process of claim 49 wherein said temperature is on the order of 500 to 600 degrees C. or more.

21. A process for fabricating a vertical transistor on a semiconductor-on-insulator wafer consisting of an underlying substrate, an intermediate insulator layer and a top crystalline semiconductor active layer, said process comprising:

sculpting from said active layer a 3-dimensional source-channel-drain structure having horizontal and vertical surfaces and comprising a channel with a source and drain at either end of the channel;

forming a thin gate oxide layer over a section of the channel;

forming a 3-dimensional gate structure over said thin gate oxide layer;

while supporting the wafer in a plasma immersion ion implantation reactor chamber, introducing into the chamber a process gas comprising a dopant species and applying plasma source power to generate a plasma from said process gas whereby to deposit on said workpiece a film comprising said dopant species.

22. The process of claim 21 futher comprising:

setting said source power at a sufficiently high level to attain a threshold conformality of the film on the horizontal and vertical surfaces of the source-channel-drain structure.

23. The process of claim 21 further comprising:

maintaining said workpiece at a sufficiently low temperature to promote deposition of said film.

24. The process of claim 22 wherein the gate structure is formed of a polycrystalline semiconductor, and wherein a threshold conformality of the film is attained on the horizontal and vertical surfaces of the gate structure.

25. The process of claim 21 further comprising heating said wafer after deposition of the film at a sufficient temperature and for a sufficient time to drive dopant atoms from the film into the horizontal and vertical surfaces of the source-channel-drain structure.

26. The process of claim 21 wherein the high level of source power is on the order of hundreds of Watts.

27. The process of claim 21 further comprising:

establishing a desired mechanical stress in said film by applying a corresponding level of plasma bias power to the wafer during deposition of the film.

28. The process of claim 27 wherein:

if the desired mechanical stress is tensile, the corresponding level of plasma bias power is on the order of hundreds of Watts or less, generating hundreds of volts or less on the wafer; and

if the desired mechanical stress is compressive, the corresponding level of plasma bias power is on the order of thousands of Watts, generating thousands of volts on the wafer.

29. The process of claim 28 wherein:

if said vertical transistor is a P-channel device, then said desired stress is compressive; and

if said vertical transistor is an N-channel device, then said desired stress is tensile.

30. The process of claim 21 further comprising applying a minimal level of RF plasma bias power.

31. The process of claim 30 wherein said minimal level is zero.

32. The process of claim 23 wherein the temperature of the workpiece is on the order of 20 degrees C.

33. The process of claim 25 wherein the heating step comprises heating the wafer to a temperature on the order of 1000 degrees C. for on the order of 10 seconds.

34. The process of claim 21 wherein said process gas further comprises a deposition material precursor species comprising at least one of (a) a precursor for a dielectric film, (b) a semiconductor species, wherein said film comprises one of (a) a dielectric material, (b) a semiconducotor material, said film being doped with said dopant species.

35. The process of claim 34 wherein the step of introducing the process gas comprises establishing a gas flow rate of the dopant species containing gas relative to a gas flow rate of the deposition material precursor gas that is sufficient to establish a dopant concentration in the dielectric material film that is at least as great as a desired dopant concentration in the source-channel-drain structure.

36. The process of claim 35 wherein the dopant concentration in the dielectric precursor material film exceeds the desired dopant concentration of the source-channel-drain structure.

37. The process of claim 35 wherein the dopant concentration in the dielectric material film is on the order of about 1E20 to 1E22/cc.

38. The process of claim 35 wherein the gas flow rate of the dopant species containing gas is on the order of about 5% of the gas flow rate of the dielectric material precursor gas.

39. The process of claim 38 wherein the deposition material precursor gas comprises one of silane, a hydrocarbon or a fluorocarbon and at least one of oxygen and nitrogen.

40. The process of claim 39 wherein the dopant containing gas comprises one of B2H6, BF3, PH3, PF3, AsH3, AsF5, AsF3, PH5.

41. The process of claim 21 wherein said film is at least a nearly pure formation of the dopant species, wherein said process gas is predominantly or purely a dopant species containing gas.

42. The process of claim 41 wherein the dopant species containing gas comprises one of B2H6, BF3, PH3, PF3, AsH3, AsF5, AsF3, PH5.

43. The process of claim 21 wherein said film is deposited to a thickness is on the order of magnitude of about 200 angstroms.

46. The process of claim 21 further comprising ion implanting dopant atoms from the plasma during deposition of the film.

47. The process of claim 46 further comprising heating the wafer to drive in dopant atoms from the film into the vertical transistor and to anneal the ion implanted atoms.

48. The process of claim 47 further comprising performing ion implantation of dopant species into said vertical transistor structure prior to deposition of said film, wherein the heating step drives ion implanted atoms further below the surfaces of the vertical transistor.