Capacitor having an anodic metal oxide substrate

• US 20050136609A1
• Filed: 08/24/2004
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mosley, Larry E., Palanduz, Cengiz A.
• Granted Patent: US 7,242,073 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01G 4/10 Metal-oxide dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances

Abstract

In one embodiment, a structure and method including an anodic metal oxide substrate used to form a capacitor are described herein.

Claims

1. A method of forming a capacitor, comprising:

anodizing at least a portion of a metal plate to form a plurality of nanopores and an insulating oxide layer;

depositing a conductive material in the plurality of nanopores to produce a plurality of nanowires and on the portion of the metal plate to form a conductive layer electrically connecting the plurality of nanowires, with the plurality of nanowires and the conductive layer being electrically isolated from the metal plate by the insulating oxide layer;

forming a first electric connection to the metal plate; and

forming a second electrical connection to the conductive layer.

5. The method according to claim 1, wherein the forming of the first plurality of protective coatings includes uniformly distributing the first plurality of protective coatings on the portion of the metal plate.

6. The method according to claim 1, further comprising:

prior to the anodizing of the metal plate, depositing a protective coating on the portion of the metal plate;

forming a first plurality of openings in the protective coating to expose a plurality of unprotected areas of the metal plate to the anodizing of the metal plate so as to produce a plurality of input/output signal vias;

the forming of the first electric connection to the metal plate further includes forming a second plurality of openings in the protective coating after the anodization of the metal plate to provide a plurality of first terminals disposed on the metal plate; and

the forming of the second electrical connection with the conductive layer further includes forming a plurality of second terminals disposed on the conductive layer.

7. The method according to claim 6, further comprising:

removing the oxide from the metal plate in the plurality of unprotected areas to form a plurality of enlarged nanopores, each of the enlarged nanopores forming one of the input/output signal vias;

anodizing the metal plate for a second time to form an oxide layer in each of the enlarged nanopores; and

depositing a plurality of input/output conductors in the plurality of enlarged nanopores.

8. The method according to claim 6, wherein the forming of the protective coating containing the first plurality of openings includes depositing a photoresist layer on the portion of the metal plate and then exposing and removing the photoresist layer in a plurality of locations to form the first plurality of openings.

9. The method according to claim 6, wherein the forming of the protective coating with the first plurality of openings includes uniformly distributing the first plurality of openings on the portion of the metal plate.

10. The method according to claim 1, further comprising:

prior to the anodizing of the metal plate, depositing a protective coating on a pair of opposed sides of the metal plate,

forming a first plurality of openings in the protective coating to expose a plurality of unprotected areas of the metal plate during the anodizing of the metal plate;

the forming of the first electric connection with the metal plate further includes forming a second plurality of openings in the protective coating after the anodizing of the metal plate to provide a plurality of first terminals disposed on the metal plate; and

the forming of the second electrical connection with the plurality of nanowires further includes forming a plurality of second terminals disposed on the conductive material.

12. The method according to claim 1, further comprising:

laminating the capacitor to a chip carrier.

2. The method according to claim 2, further comprising:

prior to the anodizing of the metal plate, forming a first plurality of protective coatings on the portion of the metal plate;

the forming of the first electric connection to the metal plate further includes opening the first plurality of protective coatings after the anodizing of the metal plate to form a plurality of first terminals disposed on the metal plate; and

the forming of the second electrical connection with the conductive layer further includes forming a plurality of second terminals disposed on the conductive layer.

3. The method according to claim 2, wherein the forming of the first plurality of protective coatings includes depositing a photoresist layer on the portion of the metal plate and then exposing and removing the photoresist layer to leave the first plurality of protective coatings.

4. The method according to claim 2, further comprising:

forming a second plurality of protective coatings onto the portion of the metal plate;

opening the centers of the second plurality of protective coatings prior to the anodizing of the metal plate to allow for formation of a plurality of holes in the metal plate during the anodizing of the metal plate; and

depositing a plurality of input/output signal conductors in the plurality of holes.

11. The method according to claim 11, further comprising:

removing the oxide from the metal plate in the plurality of unprotected areas to form a plurality of enlarged nanopores, each of the enlarged nanopores forming one of the input/output signal vias;

anodizing the metal plate for a second time to form an oxide layer in each of the enlarged nanopores; and

depositing a plurality of input/output conductors in the plurality of enlarged nanopores.

13. An electronic assembly, comprising:

an integrated circuit chip;

a capacitor coupled to the integrated circuit chip, the capacitor comprising;

a metal plate including at least an anodized portion having a surface with a plurality of nanopores;

an oxide layer formed on the surface and in the plurality of nanopores; and

a metal core;

a plurality of nanowires disposed in the plurality of nanopores;

a conductive layer formed on the surface and attached to the plurality of nanowires;

at least one first terminal electrically coupled to the metal core; and

at least one second terminal electrically coupled to the conductive layer; and

a chip carrier coupled to the integrated circuit chip and the capacitor.

14. The electronic assembly according to claim 13, further comprising a laminated layer including the capacitor;

and the laminated layer being laminated to the chip carrier.

15. The electronic assembly according to claim 13, further comprising:

a plurality of protective coatings formed on the core metal and disposed within the anodized portion;

the at least one first terminal includes a plurality of the first terminals formed within a plurality of openings in the protective coatings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

16. The electronic assembly according to claim 15, wherein the plurality of protective coatings are uniformly distributed on the surface of the anodized portion.

17. The electronic assembly according to claim 13, further comprising:

a protective coating formed on the metal core and disposed within the anodized portion, with the protective coating including a first plurality of openings arranged to expose the metal core with each of the first plurality of openings containing a signal via;

the protective coating including a second plurality of openings arranged to expose the metal core, with the at least one first terminal includes a plurality of the first terminals formed within the second plurality of openings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

18. The electronic assembly according to claim 17, wherein the first plurality of openings are uniformly distributed on the surface of the anodized portion.

19. The electronic assembly according to claim 13, wherein the metal plate comprises an anodic metal oxide substrate having a metal core, a pair of opposed surfaces with the plurality of nanopores disposed to extend between the opposed surfaces and to traverse the metal core;

and an oxide layer formed on the opposed surfaces and in the plurality of nanopores.

20. The electronic assembly according to claim 19, further comprising:

a plurality of protective coatings formed on the metal core and disposed on the pair of opposed surfaces;

the at least one first terminal includes a plurality of the first terminals formed within a plurality of openings in the protective coatings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

21. The electronic assembly according to claim 19, further comprising:

a protective coating formed on the metal core and disposed on the pair of opposed surfaces, the protective coating including a first plurality of openings arranged to expose the metal core with each of the first plurality of openings containing a signal via;

the protective coating including a second plurality of openings arranged to expose the metal core, with the at least one first terminal includes a plurality of the first terminals formed within the second plurality of openings; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

22. The electronic assembly according to claim 34, wherein an input/output conductor is disposed in each of the signal vias.

23. A system, comprising:

an electronic assembly including a processor die and a chip carrier having a laminated layer with an embedded capacitor;

the capacitor including an anodic metal oxide substrate having a plurality of nanopores formed therein;

a plurality of nanowires disposed in the plurality of nanopores;

a core metal plate;

a plurality of insulating sidewall oxide layers formed in the nanopores;

at least two first terminals disposed on the metal plate with one of the first terminals being coupled to the processor die and the other first terminal being coupled to the chip carrier; and

at least two second terminal electrically coupled to the plurality of nanowires with one of the second terminals being coupled to the processor die and the other of the second terminals being coupled to the chip carrier;

a printed circuit board (PCB) including a bus coupled to the chip carrier; and

a mass storage device coupled to the bus.

24. The system according to claim 23, further comprising an input/output network interface module coupled to the bus and a memory coupled to the bus.

25. The system according to claim 24, wherein the system is a selected one of a set-top box, an entertainment unit and a DVD player.

26. The system according to claim 23, wherein the capacitor includes an insulating outer oxide layer formed on a pair of opposed sides of the core metal plate and integrally formed with the sidewall oxide layers of the nanopores;

a conductive layer of conductive material disposed on the outer oxide layer; and

the nanowires formed of the conductive material and integrally formed with the conductive layer.

27. The system according to claim 26, wherein the capacitor further includes a plurality of protective coating formed on the pair of opposed sides of the core metal plate;

the at least one first terminal includes a plurality of the first terminals formed by a plurality of openings in the protective coatings to the core metal plate; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

28. The system according to claim 26, wherein the capacitor further includes a protective coating formed on the pair of opposed sides of the core metal plate with a first plurality of openings to the metal core;

the at least one first terminal includes a plurality of the first terminals formed by a second plurality of openings in the protective coating to the core metal plate; and

the at least one second terminal includes a plurality of the second terminals disposed on the conductive layer.

29. The system according to claim 28, further comprising a plurality of signal vias formed in the core metal plate within the first plurality of openings.

30. The system according to claim 26, wherein the capacitor has a chip side adjacent to the processor die and a bottom side adjacent to the chip carrier;

a first portion of the plurality of the first terminals are mounted on the chip side and are coupled to the processor die and a second portion of the first terminals are mounted on the bottom side and are coupled to the chip carrier;

a first portion of the plurality of the second terminals are mounted on the chip side and are coupled to the processor die and a second portion of the second terminals are mounted on the bottom side and are coupled to the chip carrier; and

a plurality of input/output conductors, coupled to the processor die and the chip carrier, disposed in a plurality of holes traversing the capacitor.