Providing access to auxiliary hardware in multiprocessor devices

• US 20050136992A1
• Filed: 12/23/2003
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mueller, Peter D.
• Application Number:
  US10/744,623
• Publication Number:
  US 20050136992A1
• Time in Patent Office: Days
• US Class Current: 455/574
• CPC Class Codes: H04M 1/2535 adapted for voice communication over an Internet Protocol [IP] network Voice over Internet Protocol (VoIP) network equipment and services H04M7/006; implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP] H04L69/16
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An auxiliary hardware device may be shared between two processors in a mobile device, for example, to reduce power consumption. As one example, the auxiliary hardware device may be a codec. The processors may have an interface to independently access the auxiliary hardware device. As a result, it may be unnecessary to power up both processors to access the shared auxiliary hardware device.

Claims

1. A method comprising:

enabling an auxiliary hardware device to be directly accessed by two processors of a mobile system.

2. The method of claim 1 including enabling at least one processor to determine whether the other processor is powered up.

3. The method of claim 2 including, if the other processor is not powered up, directly accessing the auxiliary hardware device.

4. The method of claim 2 including, if the other processor is powered up, accessing the auxiliary hardware device through the other processor.

5. The method of claim 1 including sharing the auxiliary hardware device between a baseband processor and an application processor.

6. The method of claim 1 including sharing a codec between the two processors.

7. The method of claim 1 including sharing an encryption/decryption engine between two processors.

8. The method of claim 1 including allowing two processors to share a graphics accelerator.

9. The method of claim 1 including allowing two processors to share a display controller.

10. The method of claim 1 including allowing two processors to share a camera.

11. The method of claim 1 including allowing two processors to access said auxiliary hardware device through two separate ports or a single shared port.

12. A system comprising:

a first processor;

a second processor;

an auxiliary hardware device including at least two ports, one port for said first processor and the other port for said second processor; and

a static random access memory.

13. The system of claim 12 wherein said system is a mobile system.

14. The system of claim 12 wherein said system is an embedded system.

15. The system of claim 12 wherein said first processor is an application processor and said second processor is a baseband processor.

16. The system of claim 12 wherein said auxiliary hardware device is a codec.

17. The system of claim 12 wherein said auxiliary hardware device is an encryption/decryption engine.

18. The system of claim 12 wherein said auxiliary hardware device is a display controller.

19. The system of claim 12 wherein said auxiliary hardware device is a camera controller.

20. The system of claim 12 wherein said auxiliary hardware device is a graphics accelerator.

21. The system of claim 12 wherein said system to implement voice over Internet Protocol communications.

22. The system of claim 12 wherein said system to implement cellular communications.

23. An article comprising a medium storing instructions that, if executed, enable a first processor to:

determine whether an auxiliary hardware device is available;

if so, determine whether a second processor is powered up; and

if not, directly access said auxiliary hardware device.

24. The article of claim 23 further storing instructions that, if executed, enable the first processor to access said auxiliary hardware device through said second processor if said second processor is powered up.

25. The article of claim 23 further storing instructions that, if executed, enable the first processor to directly access an auxiliary device in the form of a graphics accelerator.

26. The article of claim, 23 further storing instructions that, if executed, enable the first processor to selectively directly access the auxiliary hardware device or access the auxiliary hardware device through the second processor.

27. The article of claim 23 further storing instructions that, if executed, enable the first processor to implement voice over Internet Protocol.

28. The article of claim 23 further storing instructions that, if executed, enable the first processor to implement cellular communications.

29. A system comprising:

a first processor;

a second processor; and

an auxiliary hardware device including at least two ports, one port for said first processor and the other port for said second processor.

30. The system of claim 29 wherein said first processor is an application processor and said second processor is a baseband processor.

31. The system of claim 29 wherein said auxiliary hardware device is a codec.