Network interface and protocol

• US 20050138242A1
• Filed: 09/15/2003
• Published: 06/23/2005
• Est. Priority Date: 09/16/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx Technology Ltd. (Advanced Micro Devices, Inc.)
• Inventors: Clarke, David Julian, Roberts, Derek Edward, Riddoch, David James, Pope, Steve Leslie
• Granted Patent: US 7,844,742 B2
• Time in Patent Office: Days
• US Class Current: 710/48
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/545 where tasks reside in different layers, e.g. user- and kernel-space
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/35 involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function

Abstract

A communication interface for providing an interface between a data link and a data processor, the data processor being capable of supporting an operating system and a user application, the communication interface being arranged to: support a first queue of data received over the link and addressed to a logical data port associated with a user application; support a second queue of data received over the link and identified as being directed to the operating system; and analyse data received over the link and identified as being directed to the operating system or the data port to determine whether that data meets one or more predefined criteria, and if it does meet the criteria transmit an interrupt to the operating system.

Claims

1. A communication interface for providing an interface between a data link and a data processor, the data processor being capable of supporting an operating system and a user application, the communication interface being arranged to:

support a first queue of data received over the link and addressed to a logical data port associated with a user application;

support a second queue of data received over the link and identified as being directed to the operating system; and

analyse data received over the link and identified as being directed to the operating system or the data port to determine whether that data meets one or more predefined criteria, and if it does meet the criteria transmit an interrupt to the operating system.

2. A communication interface as claimed in claim 1, wherein the user application has an address space and the first queue is located in that address space.

3. A communication interface as claimed in claim 1, wherein the operating system has an address space and the second queue is located in that address space.

4. A communication interface as claimed in claim 3, wherein the user application and the operating system have the same address space.

5. A communication interface as claimed in claim 1, the communication interface being arranged apply to the first queue data received over the link and identified as being directed to the data port.

6. A communication interface as claimed in claim 1, the communication interface being arranged apply to the second queue data received over the link and identified as being directed to the operating system.

7. A communication interface as claimed in claim 1, wherein one of the predefined criteria is such that if the data received over the link matches one or more predetermined message forms then the communication interface will transmit an interrupt to the operating system.

8. A communication interface as claimed in claim 1, wherein the communication interface is arranged to, if the data meets one or more of the predefined criteria and one or more additional criteria, transmit an interrupt to the operating system and transmit a message to the operating system indicating a port to which the data was addressed.

9. A communication interface as claimed in claim 8, wherein the additional criteria are indicative of an error condition.

10. A communication interface as claimed in claim 1, wherein the communication interface is arranged to support a third queue of data received over the link and addressed to a logical data port associated with a user application, and is arranged to apply to the first queue data units received over the link and of a form having a fixed length and to apply to the third queue data units received over the link and of a form having a variable length.

11. A communication interface as claimed in claim 10, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating an error status.

12. A communication interface as claimed in claim 10, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating a request for or acknowledgement of set-up of a connection.

13. A communication interface as claimed in claim 10, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating a data delivery event.

14. A communication interface as claimed in claim 1, wherein the communication interface is arranged to analyse the content of each data unit received over the link and to determine in dependence on the content of that data unit which of the said queues to apply the data unit to.

15. A communication interface as claimed in claim 1, wherein the communication interface is configurable by the operating system to set the said criteria.

16. A communication interface as claimed in claim 1, wherein one or both of the communication interface and the operating system is responsive to a message of a predetermined type to return a message including information indicative of the status of the port.

17. A communication system including a communication interface as claimed in claim 16, and the data processor, the data processor being arranged to, when the processing of an application with which a data port is associated is suspended, set the criteria such that the communication interface will transmit an interrupt to the operating system on receiving data identified as being directed to that data port.

39. A communication interface as claimed in claim 1.

40. A communication system as claimed in claim 17.

18. A communication interface for providing an interface between a data link and first data processing apparatus including a memory, the data interface being such that a region of the memory of the first data processing apparatus can be mapped on to memory of a second data processing apparatus connected to the communication interface by the link, the communication interface being arranged to, on establishing a mapping of a first range of one or more memory locations in the second data processing apparatus on to a second range of one or more memory locations in the first data processing apparatus, transmit to the second data processing apparatus data identifying the first range of memory locations.

19. A communication interfaces as claimed in claim 18, wherein the said one or more memory locations in the memory of the first data processing apparatus are one or more virtual memory locations and the communication interface is arranged to, on establishing the said mapping, establish a further mapping of the one or more virtual memory locations on to one or more physical memory locations in the memory of the first data processing apparatus.

20. A communication interface as claimed in claim 18, wherein the communication interface is arranged to, on establishing a mapping of a first range of one or more memory locations in the memory of the second data processing apparatus on to a second range of one or more memory locations in the memory of the first data processing apparatus, allocate an identity to that mapping and transmit that identity to the second data processing apparatus.

21. A communication interface as claimed in claim 18, wherein the communication interface is capable of communicating by means of data messages which specify a destination port to which data they contain is to be applied.

22. A communication interface as claimed in claim 18, wherein the communication interface is arranged to, on establishing a mapping of a first range of one or more memory locations in the memory of the second data processing apparatus on to a second range of one or more memory locations in the memory of the first data processing apparatus, determine check data and transmit the check data to the second data processing apparatus, and wherein the communication interface is arranged to reject subsequent communications over the mapping which do not indicate the check data.

23. A communication interface as claimed in claim 22, wherein the check data is randomly generated by the communication interface.

24. A communication interface as claimed in claim 22, wherein to indicate the check data a communication includes the check data.

25. A communication interface as claimed in claim 22, wherein the communication interface is arranged to modify the check data, according to a predefined scheme, during the operation of the mapping.

26. A communication interface as claimed in claim 25, wherein the check data represents a number and the predefined scheme is to increment the number represented by the check data by a predefined amount each time a predefined number of communications over the mapping are accepted.

27. A communication interface as claimed in claim 18, wherein the communication interface is arranged to reject subsequent communications over the mapping which indicate a request for accessing data outside the first range.

28. A communication interface as claimed in claim 19, wherein the communication interface is capable of supporting a plurality of mappings each of a respective first range of one or more virtual memory locations in the second data processing apparatus on to a respective second range of one or more memory locations in the first data processing apparatus, and for each such mapping a respective further mapping of the respective one or more virtual memory locations on to one or more physical memory locations in the memory of the first data processing apparatus.

29. A communication interface as claimed in claim 28, comprising a translation interface for translating accesses to or from each of the said ranges of one or more virtual memory locations into accesses to or from the respective one or more physical memory locations in the memory of the first data processing apparatus and for translating accesses to or from each of the one or more physical memory locations in the memory of the first data processing apparatus into accesses to or from the respective ranges of one or more virtual memory locations.

30. A communication interface as claimed in claim 29, comprising a mapping memory arranged to store specifications of the said further mappings.

31. A communication interface as claimed in claim 30, wherein the mapping memory comprises a first mapping memory local to the translation interface, and a second mapping memory less local to the translation interface than the first mapping memory, and wherein the communication interface is arranged to store specifications of all of the further mappings in the second mapping memory, and to store specifications of only some of the further mappings in the first mapping memory.

32. A communication interface as claimed in claim 31, wherein the first mapping memory is an associative memory.

33. A communication interface as claimed in claim 31, wherein the translation interface is arranged to, in order to translate between an access to or from one of the said ranges of one or more virtual memory locations and an access to or from the respective one or more physical memory locations in the memory of the first data processing apparatus, preferentially access the first mapping memory to implement the translation, and if the specification of the mapping of the range of virtual memory locations the subject of the access is not stored in the first mapping memory to access the second mapping memory to implement the translation.

34. A communication interface as claimed in claim 31, wherein the communication interface is arranged to store specifications of the most recently used further mappings in the first mapping memory.

35. A communication system including a communication interface as claimed in claim 18, and the data processor, the data processor being capable of supporting an operating system and a user application, and the system comprising a data store which stores items of data defining operation parameters for communications over the data link to transmit data stored in the first range or receive data for storage in the first range.

36. A communication system as claimed in claim 35, wherein the operating system is arranged to permit a user application to access one or more items of data in the data store dependent on a level of trust granted to the application.

37. A communication system as claimed in claim 36, wherein the check data is stored as one of the items of data in the data store, the operating system is arranged to permit at least some user applications to have write access to that item of data, and the communication interface is arranged to, in order to determine the check data, read the content of that item of data and treat it as the check data.

38. A communication system as claimed in claim 36, wherein items of data in the data store define the start and end points of the first range of memory locations in the memory of the first data processing apparatus and store the start and end points of the second range of memory locations in the memory of the second data processing apparatus, and the operating system is arranged to permit applications having one or more levels of trust to have write access to the items of data in the data store that second, and store the start and end points of the second range of memory locations in the memory of the second data processing apparatus and to permit no applications to have write access to the items of data in the data store that define the start and end points of the first range of memory locations in the memory of the first data processing apparatus.