Integral memory buffer and serial presence detect capability for fully-buffered memory modules

• US 20050138267A1
• Filed: 12/23/2003
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S., Ellis, Robert M., Freeman, Chris B., Halbert, John B., Williams, Michael W.
• Application Number:
  US10/746,948
• Publication Number:
  US 20050138267A1
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.

Claims

1. A memory module buffer comprising:

a host-side memory channel interface and a downstream memory channel interface capable of communicating with other devices across memory channels;

a memory device interface coupled at least to the host-side memory channel interface, to communicate with memory devices on a memory module on behalf of a device communicating with the buffer over the host-side memory channel interface;

a serial bus port;

a nonvolatile memory area to store information relating to a memory module served by the buffer; and

a first serial bus controller to transmit information from the nonvolatile memory area out the serial bus port in response to requests received at the serial bus port.

2. The memory module buffer of claim 1, further comprising a second serial bus controller, connected to the serial bus port, to activate memory module buffer functions in response to serial bus commands.

3. The memory module buffer of claim 2, wherein the first serial bus controller responds to a first serial bus address and the second serial bus controller responds to a second serial bus address.

4. The memory module buffer of claim 3, wherein the first and second serial bus controllers comprise at least partially shared common serial bus receiver/driver circuitry.

5. The memory module buffer of claim 1, further comprising a second memory area accessible to both the first serial bus controller and to a self-test function of the buffer, the nonvolatile memory area accessible from the serial bus port using addresses selected from a first range of memory addresses, the second memory area accessible from the serial bus port using addresses selected from a second range of memory addresses.

6. The memory module buffer of claim 1, wherein the first serial bus controller responds to an assigned serial bus address, wherein at least a portion of the assigned serial bus address is supplied to the controller through one of the memory channel interfaces.

7. The memory module buffer of claim 1, wherein the nonvolatile memory area is accessible to the memory device interface through a data channel internal to the memory module buffer.

8. The memory module buffer of claim 7, further comprising a set of configuration registers, wherein the internal data channel is used to mirror information from the nonvolatile memory area to the configuration registers upon startup.

9. The memory module buffer of claim 1, wherein the nonvolatile memory area comprises a plurality of data storage cells selected from the group of storage cell types including masked read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable read-only memory (EEPROM), flash EEPROM, laser-cut fuses, and combinations thereof.

10. The memory module buffer of claim 1, comprising first and second integrated circuits packaged in a common package, wherein the nonvolatile memory area and first serial bus controller are integrated on the first integrated circuit and the memory channel interfaces and memory device interface are integrated on the second integrated circuit, the second integrated circuit further comprising a second serial bus controller, wherein the first and second serial bus controllers both connect to the serial bus port.

11. A buffered memory module comprising:

a plurality of memory devices; and

a memory module buffer coupled to the memory devices, the memory module buffer comprising a serial presence detect function for the module.

12. The buffered memory module of claim 11, wherein the serial presence detect function comprises a nonvolatile memory area containing information related to the memory devices, a serial bus port, and a first serial bus controller to transmit information from the nonvolatile memory area out the serial bus port in response to requests received at the serial bus port.

13. The buffered memory module of claim 12, further comprising a plurality of address assignment lines connected to the first serial bus controller to inform the serial bus controller of a memory slot assignment.

14. The buffered memory module of claim 12, wherein the first serial bus controller responds to a serial bus address at least partially dependent on a memory slot assignment, wherein the memory slot assignment is communicated to the memory module buffer over a memory channel.

15. The buffered memory module of claim 12, further comprising a second serial bus controller connected to the serial bus port, and a built-in self test function, the second serial bus controller providing access between the serial bus port and the built-in self test function.

16. The buffered memory module of claim 12, wherein the memory module buffer comprises first and second integrated circuits packaged in a common package, wherein the nonvolatile memory area and the first serial bus controller are integrated on the first integrated circuit, the memory module buffer further comprising host-side and downstream memory channel interfaces and a memory device interface integrated on the second integrated circuit, the second integrated circuit further comprising a second serial bus controller, wherein the first and second serial bus controllers both connect to a common serial bus port

17. A method of assigning a serial bus address to a serial presence detect function on a buffered memory module, the method comprising:

transmitting a memory slot assignment to the buffered memory module over a memory channel; and

based at least in part on the transmitted memory slot assignment, asserting, internal to the module, an assigned serial bus address to the serial presence detect function.

18. The method of claim 17, wherein transmitting a memory slot assignment to the buffered memory module comprises transmitting a first memory slot assignment token over a first memory channel segment, and receiving the first memory slot assignment token at the buffered memory module.

19. The method of claim 18, further comprising the buffered memory module passing the first memory slot assignment token back along the first memory channel segment.

20. The method of claim 18, further comprising the buffered memory module incrementing a counter in the first memory slot assignment token to form a second memory slot assignment token, and passing the second memory slot assignment token forward along a second memory channel segment.

21. The method of claim 18, further comprising the buffered memory module disabling forwarding out a second memory channel segment of data received on the first memory channel segment until the first memory slot assignment token is received.

22. A computing device comprising:

a processor;

a host memory controller in communication with the processor;

at least a first buffered memory module, comprising a plurality of memory devices, and a memory module buffer coupled to the plurality of memory devices, the memory module buffer having a serial presence detect function;

a first point-to-point memory channel connecting the host memory controller to the first buffered memory module;

a relatively low-speed bus coupled to the first buffered memory module serial presence detect function to allow the processor to discover information related to the memory module configuration.

23. The computing device of claim 22, further comprising:

a second buffered memory module comprising a plurality of memory devices and a memory module buffer coupled to the plurality of memory devices, the second buffered memory module having a serial presence detect function; and

a second point-to-point memory channel connecting the first buffered memory module to the second buffered memory module;

wherein the relatively low-speed bus is also coupled to the second buffered memory module serial presence detect function.

24. The computing device of claim 22, wherein the serial presence detect function on the first memory module comprises a serial bus controller and a nonvolatile memory area accessible through the serial bus controller, the nonvolatile memory area containing information related to the memory devices on that memory module.

25. The computing device of claim 24, the nonvolatile memory area further containing information related to the capabilities of the memory module buffer.

26. The computing device of claim 22, wherein the serial bus controller responds to a serial bus address that is configurable using commands issued to the memory module buffer across the first memory channel.