Rotational use of memory to minimize write cycles

• US 20050138271A1
• Filed: 12/17/2003
• Published: 06/23/2005
• Est. Priority Date: 12/17/2003
• Status: Active Grant

• Current Assignee: Wegener Communications, Inc. (Wegener Corporation)
• Original Assignee: Wegener Communications, Inc. (Wegener Corporation)
• Inventors: Gelsomini, Anthony L., Bernstein, Sacha
• Granted Patent: US 7,480,760 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A system and method to minimize the number of erase cycles performed on a flash memory device to extend its useful life. A flash memory device has several areas where data is stored. Each area is referred to as a block. Memory usage is rotated between blocks to evenly distribute erase cycles.

Claims

1. A method for managing erasures on a flash memory device having addressable physical sections organized as blocks, the method comprising the steps of:

a. identifying a first current block;

b. identifying a first available record in said first current block;

c. writing a first flag in a first header in said first available record;

d. writing data consecutively after said first header;

e. identifying a subsequent available record;

f. writing a second flag in a second header in said subsequent available record; and

g. writing a first pointer to said first header, wherein said first pointer indicates an address for superceded data.

2. The method according to claim 1, wherein said first pointer is equal to a length of said data written consecutively after said first header.

3. The method according to claim 1, further comprising the step of erasing said first current block.

4. The method according to claim 1, further comprising the step of writing data consecutively after said second header.

5. The method according to claim 4, further comprising the step of writing a second pointer to said second header.

6. The method according to claim 1, further comprising the step of identifying a second current block.

7. The method according to claim 6, further comprising the step of erasing said second current block.

8. The method according to claim 1, further comprising the step of reading a block state of said first current block or said second current block.

9. The method according to claim 8, wherein said block state is selected from the group consisting of full, partially full, and erased.

10. A system for flash memory having addressable locations organized as blocks, comprising:

a. a flash driver having flash abstraction logic, said flash abstraction logic configured to;

i. identify a first current block;

ii. identify a first available record in said first current block;

iii. write a first flag in a first header in said first available record;

iv. write data consecutively after said first header;

v. identify a subsequent available record;

vi. write a second flag in a second header in said subsequent available record; and

vii. write a first pointer to said first header, wherein said first pointer indicates an address for superceded data.

11. The system according to claim 10, said flash driver further comprising programmable flash medium logic.

12. The system according to claim 10, further comprising a flash memory device, said flash memory device comprising:

a. a memory array with a plurality of floating gate memory cells arranged in at least two erase blocks, each of said at least two erase blocks having a plurality of records, and each record including a data section and a node header; and

b. a control circuit, said control circuit configured to write data consecutively in a first current block of said at least two erase blocks until it is full and subsequently to write consecutively in one other of said at least two erase blocks.

13. The system according to claim 12, wherein each of said at least two erase blocks has 128K records.

14. The system according to claim 12, wherein said node header is 16 bit type.

15. The system according to claim 12, wherein said node header is 24 bit type.

16. The system according to claim 12, further comprising architecture for error checking.

17. In a flash memory device having a first block and a second block, a method of rotating between the first memory block and the second memory block to extend the useful life of the flash memory, the method comprising the steps of:

a) erasing the first block and the second block;

b) identifying a first open record in the first block;

c) writing a previous header in said first open record;

d) writing data consecutively after said previous header;

e)) identifying a subsequent open record in the first block;

f) writing a subsequent header to said subsequent open record;

g) writing data consecutively after said subsequent header;

h) writing a data length variable to said previous header;

i) iteratively performing steps “

e,”

“

f,”

“

g,” and

“

h”

until there are no more open records in the first block; and

h) identifying a first open record in the second block.

18. The method according to claim 17, further comprising the steps of:

a) writing a previous header in said first open record in the second block; and

b) writing data consecutively after said previous header.

19. The method according to claim 18, further comprising the step of erasing the first block.

20. The method according to claim 19, further comprising the steps of:

a) identifying a subsequent open record in the second block;

b) writing a subsequent header to said subsequent open record;

c) writing data consecutively after said subsequent header;

d) writing a data length variable to said previous header; and

i) iteratively performing steps “

a,”

“

b,”

“

c,” and

“

d”

until there are no more open records in the second block.