Method and apparatus for logic analyzer observability of buffered memory module links

• US 20050138302A1
• Filed: 12/23/2003
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lusk, John B., Raza, Ishfaqur, Glass, Richard J.
• Application Number:
  US10/746,532
• Publication Number:
  US 20050138302A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

Some embodiments of the invention maintain a high degree of overall logic analysis and debug capabilities while simultaneously enabling the reduction of logic analyzer design complexity. Other embodiments of the invention provide a logical analyzer interface (LAI) mode of operation to memory module buffers by adding additional LAI features to the silicon designed to also operate in a normal mode. Other embodiments of the invention are described in the claims.

Claims

1. A method comprising:

coupling a logic analyzer interface (LAI) having a first buffer to a buffered memory system;

coupling a first buffered memory module having a second buffer to the LAI; and

analyzing data traffic between the second buffer operating in a normal mode and a component of the buffered memory system using the first buffer operating in an LAI mode.

2. The method of claim 1, wherein analyzing data traffic using the first buffer operating in the LAI mode comprises:

delaying the data traffic; and

transmitting the data traffic to a logic analyzer at a reduced data transfer rate.

3. The method of claim 2, wherein analyzing data traffic using the first buffer operating in the LAI mode further comprises:

analyzing the data traffic onboard the first buffer to generate a derived signal; and

transmitting the derived signal to the logic analyzer.

4. The method of claim 1, wherein analyzing data traffic between the second buffer operating in a normal mode and the component of the buffered memory system comprises:

analyzing data traffic between the second buffer and a host.

5. The method of claim 1, wherein analyzing data traffic between the second buffer operating in a normal mode and a component of the buffered memory system comprises:

analyzing data traffic between the second buffer and a third buffer operating in the normal mode on a second buffered memory module.

6. The method of claim 5, wherein the first and second buffered memory modules are dual inline memory modules each having a plurality of memory chips.

7. The method of claim 6, wherein the plurality of memory chips comprise a plurality of DRAM devices.

8. The method of claim 1, further comprising:

capturing data traffic with the first buffer operating in the LAI mode and retransmitting the data to the second buffer operating in the normal mode and the component of the buffered memory subsystem.

9. The method of claim 1, wherein analyzing data traffic comprises analyzing northbound data traffic and southbound data traffic.

10. The method of claim 1, further comprising:

coupling a second logic analyzer interface (LAI) having a third buffer to the buffered memory system;

coupling a third buffered memory module having a fourth buffer to the second LAI; and

analyzing data traffic between the fourth buffer operating in the normal mode and a component of the buffered memory subsystem using the third buffer operating in the LAI mode.

11. An apparatus comprising:

a first connector configured to couple to a first memory module having a first buffer;

a second connector configured to couple to a logic analyzer probe;

a third connector configured to couple to a memory system, the memory system including a host and a second memory module having a second buffer; and

a third buffer configured to run in a logic analyzer interface mode when the first and second buffers are running in a normal mode.

12. The apparatus of claim 11, wherein the third buffer comprises:

first circuitry configured to capture and retransmit data traffic; and

second circuitry configured to analyze data traffic and configured to provide a derived signal based on the analyzed data traffic to the logic analyzer probe.

13. The apparatus of claim 12, wherein the first circuitry is configured to transmit the data traffic to the logic analyzer probe at a reduced data transfer rate.

14. The apparatus of claim 12, wherein the data traffic comprises:

southbound data traffic moving in a direction from the host to the first buffer, and

northbound data traffic moving in a direction from the first buffer to the host.

15. The apparatus of claim 12, wherein the first buffer comprises:

first circuitry and second circuitry, wherein the second circuitry is disabled through a fusing process.

16. The apparatus of claim 11, wherein the first and the second memory modules are selected from the group consisting of dual inline memory modules and single inline memory modules.

17. An apparatus comprising:

an output interface;

a memory module interface configured to connect to a first buffered memory module;

a buffer configured to capture data traffic in a memory system that includes a host and a second buffered memory module, configured to retransmit the data traffic to the first buffered memory module at a first transfer rate, and configured to retransmit the data traffic to the output interface at a second transfer rate.

18. The apparatus of claim 17, wherein the output interface comprises:

a socket configured to accept a logic probe.

19. The apparatus of claim 17, wherein the first transfer rate is greater than the second transfer rate.

20. The apparatus of claim 17, wherein the data traffic comprises:

northbound data traffic moving in a direction towards the host; and

southbound data traffic moving in a direction towards the second buffered memory module.

21. The apparatus of claim 17, wherein the buffer further comprises:

a circuit configured to analyze the data traffic and provide a signal derived from analyzed data traffic to the output interface.

22. The apparatus of claim 17, further comprising:

a memory system interface configured to couple the buffer to the memory system.

23. The apparatus of claim 22, wherein the memory system interface is a card edge connector.