MAXQ microcontroller

• US 20050138330A1
• Filed: 12/23/2003
• Published: 06/23/2005
• Est. Priority Date: 12/23/2003
• Status: Abandoned Application

• Current Assignee: Dallas Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Owens, Jeffrey D., Ma, Edward Tang K., Chenot, Tom, Loomis, Don
• Application Number:
  US10/746,877
• Publication Number:
  US 20050138330A1
• Time in Patent Office: Days
• US Class Current: 712/209
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30163 with implied specifier, e.g. top of stack
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/342 Extension of operand address space
• CPC Class Codes: G06F 9/3824 Operand accessing

Abstract

A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and the destination module to which data is to be stored. The address/data capability of an instruction word may be extended via a prefix module. If an operation is performed on the data, the source module or the destination module may perform the operation during the same clock cycle in which the data is transferred.

Claims

1. A microcontroller comprising:

at least one register module for performing instructions or storing data;

a program memory for providing read-only memory;

a data memory for providing read and write memory, wherein the data memory is separate from the program memory;

a memory management unit for supporting the program memory and the data memory;

at least one module for providing a specific functionality to the microcontroller;

a central processing unit for controlling operations of the microcontroller;

a point-to-point transport network for providing a data path between the

microcontroller, the at least one register module, the program memory, and the data memory; and

wherein an instruction word causes an instruction to be executed in a single clock cycle.

2. The microcontroller of claim 1, wherein the data memory is an SRAM memory.

3. The microcontroller of claim 1, wherein the memory management unit is capable of merging different physical memories in different memory spaces into one linear memory space.

4. The microcontroller of claim 1, wherein the at least one register module comprises:

at least one special purpose register module providing central processing unit (CPU) instructions necessary for the microcontroller; and

at least one special function register module for providing unique user functions or peripherals.

5. The microcontroller of claim 4, wherein the at least one special purpose register comprises a prefix module for expanding address or data capabilities of an instruction word.

6. The microcontroller of claim 4, wherein the at least one special purpose register comprises a pointer module for indirect accessing.

7. The microcontroller of claim 4, wherein the at least one special purpose register comprises an accumulator module.

8. The microcontroller of claim 7, further comprising:

an arithmetic logic unit (ALU) and an array of registers capable of being automatically activated as the an active accumulator for ALU operation in a programmable modulo fashion.

9. The microcontroller of claim 4, wherein the at least one register module is operable as the at least one special function register for providing a special functionality to the microcontroller.

10. The microcontroller of claim 9, wherein the register module is a serial port.

11. The microcontroller of claim 9, wherein the register module is an analog-to-digital converter.

12. The microcontroller of claim 9, wherein the register module is an external processing device.

13. The microcontroller of claim 1, wherein the register module executes the instruction prior to transmitting data to a second register module.

14. The microcontroller of claim 1, wherein the register module executes the instruction subsequent to receiving data from a second register module.

15. The microcontroller of claim 1, wherein the transport network provides a system data path and establishes a point-to-point connection between the CPU, the at least one register module, the data memory, and the program memory.

16. The microcontroller of claim 1, further comprising a decoder for decoding at least a portion of the instruction.

17. An instruction for causing execution of a command, the instruction comprising:

a source operand for indicating a source module from which data is retrieved;

a destination operand for indicating a destination module to which data is transmitted; and

a format bit for indicating whether the instruction is an immediate source instruction or a register source instruction.

18. The instruction of claim 17, wherein the source operand includes 8 bits.

19. The instruction of claim 18, wherein the source operand comprises:

a source identifier identifying the source module that is the source of data for the instruction; and

a sub-decode portion for indicating an operational code or an index for a register of the source module.

20. The instruction of claim 18, wherein the source operand may be extended via a prefix module.

21. The instruction of claim 17, wherein the destination operand includes 7 bits.

22. The instruction of claim 21, wherein the destination operand may be extended via a prefix module.

23. The instruction of claim 21, wherein the destination operand comprises:

a destination identifier identifying the destination module that is the target of data for the instruction; and

a sub-decode portion for indicating an operational code or an index for a register of the destination module.

24. A method for executing an instruction for a microcontroller, the method comprising:

fetching data from a source module;

performing an operation on the fetched data; and

storing the data at a destination module, wherein the steps of fetching, performing, and storing are executed in one clock cycle.

25. The method of claim 24, wherein the step of performing is executed at the source module.

26. The method of claim 24, wherein the step of performing is executed at the destination module.

27. The method of claim 24, wherein the step of fetching comprises the steps of:

determining from the instruction a specific source module from which the data is to be retrieved; and

determining from the instruction a specific index of the source module from which the data is to be retrieved.

28. The method of claim 24, wherein the step of fetching comprises the steps of:

determining from the instruction a specific source module from which the data is to be retrieved; and

determining from the instruction a specific operation to be performed on the data.

29. The method of claim 24, wherein the step of storing comprises the steps of:

determining from the instruction a specific destination module to which the data is to be stored; and

determining from the instruction a specific index of the destination module to which the data is to be stored.

30. The method of claim 24, wherein the step of storing comprises the steps of:

determining from the instruction a specific destination module to which the data is to be stored; and

determining from the instruction a specific operation to be performed on the data.

31. A microcontroller comprising:

a program memory for providing read-only memory;

a data memory for providing read and write memory, wherein the data memory is separate from the program memory;

at least one module for providing a specific functionality to the microcontroller;

a central processing unit for controlling operations of the microcontroller; and

wherein an instruction word causes an instruction to be executed in a single clock cycle.