In-plane switching mode liquid crystal display device

• US 20050139837A1
• Filed: 12/28/2004
• Published: 06/30/2005
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Lee, Dong Hoon, Lee, Jae Kyun
• Granted Patent: US 7,663,583 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G09G 2300/0434 Flat panel display in which a field is applied parallel to the display plane
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors

Abstract

An IPS mode LCD device is disclosed in which a common voltage drop and delay is decreased. The LCD includes gate and data lines crossing each other to define pixel regions. Thin film transistors are formed at crossing portions of the gate and data lines. Common lines are parallel with the gate lines and common electrodes project from the common lines parallel with the data lines. Pixel electrodes connected with drain electrodes of the thin film transistors are formed in the pixel regions between the parallel common electrodes. A first common voltage supplying line applies a first common voltage or a second common voltage to a closed circuit formed by grouping the adjacent odd numbered common lines. A second common voltage supplying line applies the second common voltage or the first common voltage to a closed circuit formed by grouping the adjacent even numbered common lines.

Claims

1. A substrate comprising:

a plurality of gate and data lines crossing each other, the gate and data lines defining a plurality of pixel regions;

a plurality of thin film transistors formed at crossing portions of the gate and data lines;

a plurality of common lines between the gate lines;

a plurality of common electrodes projecting from the common lines;

a plurality of pixel electrodes connected with drain electrodes of the thin film transistors, the pixel electrodes formed in the pixel regions between the common electrodes;

a first common voltage supplying line that forms a first closed circuit by grouping adjacent odd numbered common lines; and

a second common voltage supplying line that forms a second closed circuit by grouping adjacent even numbered common lines.

2. The substrate of claim 1, wherein a first common voltage applied by the first common voltage supplying line and a second common voltage applied by the second common voltage supplying line have opposite polarities.

3. The substrate of claim 2, wherein the first common voltage and the second common voltage alternate polarities each frame.

4. The substrate of claim 1, wherein the first and second common voltage supplying lines are formed on the same layer as the data lines.

5. The substrate of claim 1, wherein the first and second common voltage supplying lines are formed of the same material as the data lines.

6. The substrate of claim 1, wherein the first and second common voltage supplying lines have the same resistivity.

7. The substrate of claim 1, wherein the common electrodes are parallel with the data lines.

8. The substrate of claim 1, wherein the common lines alternate with the gate lines in a direction along which the data lines extend.

9. A liquid crystal display (LCD) comprising:

opposing substrates; and

a liquid crystal layer between the opposing substrates,

wherein one of the opposing substrates includes;

a plurality of gate and data lines crossing each other, the gate and data lines defining a plurality of pixel regions;

a plurality of thin film transistors formed at crossing portions of the gate and data lines;

a plurality of common lines parallel with the gate lines;

a plurality of common electrodes projecting from the common lines, the common electrodes parallel with the data lines;

a plurality of pixel electrodes connected with drain electrodes of the thin film transistors, the pixel electrodes formed in the pixel regions between the common electrodes;

a first common voltage supplying line that connects a first set of the common lines together at a plurality of locations along each common line of the first set of the common lines; and

a second common voltage supplying line that connects a second set of the common lines together at a plurality of locations along each common line of the second set of the common lines.

10. The LCD of claim 9, wherein the first and second set of common lines alternate in a direction along which the data lines extend.

11. The LCD of claim 9, wherein a first common voltage applied by the first common voltage supplying line and a second common voltage applied by the second common voltage supplying line have opposite polarities.

12. The LCD of claim 9, wherein the first common voltage and the second common voltage alternate polarities each frame.

13. The LCD of claim 9, wherein the first and second common voltage supplying lines are formed on the same layer as the data lines.

14. The LCD of claim 9, wherein the first and second common voltage supplying lines are formed of the same material as the data lines.

15. The LCD of claim 9, wherein the first and second common voltage supplying lines have the same resistivity.

16. The LCD of claim 9, wherein the common electrodes are parallel with the data lines.

17. The LCD of claim 9, wherein the common lines alternate with the gate lines in a direction along which the data lines extend.

18. A method comprising:

forming gate lines;

forming common lines;

covering the gate lines and the common lines with an insulating layer;

etching contact holes in the insulating layer;

depositing and patterning a metal layer on the insulating layer, the metal layer forming;

data lines that cross the gate lines and define pixel regions, and

common voltage supplying lines connecting, through the contact holes, a first set of the common lines together at a plurality of locations along each common line of the first set and connecting a second set of the common lines together at a plurality of locations along each common line of the second set;

coating a passivation layer on the data lines and the common voltage supplying lines;

depositing and patterning a transparent conductive material on the passivation layer, the patterned transparent conductive material forming pixel electrodes.