Method for manufacturing a power device with insulated gate and trench-gate structure having controlled channel length and corresponding device

• US 20050139913A1
• Filed: 11/23/2004
• Published: 06/30/2005
• Est. Priority Date: 11/28/2003
• Status: Abandoned Application

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Fragapane, Leonardo, Alessandria, Antonino Sebastiano
• Application Number:
  US10/996,131
• Publication Number:
  US 20050139913A1
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a semiconductor power device with an insulated gate and trench-gate structure integrated on a semiconductor substrate includes providing a body region in the semiconductor substrate, forming a surface source region on the body region, etching the semiconductor substrate and forming a trench to form the trench-gate structure. The method also includes forming a deep portion of the source region along the trench.

Claims

1. A method for manufacturing an insulated trench-gate power device integrated on a semiconductor substrate, comprising:

providing a body region in said semiconductor substrate;

forming a surface source region on said body region;

etching the semiconductor substrate;

forming a trench to form the trench-gate structure; and

forming a deep portion of the source region along the trench.

2. The method of claim 1, wherein the surface source region is formed on the semiconductor substrate around the trench simultaneously with the deep source portion.

3. The method of claim 1 further comprising forming a deep body portion extending to a predetermined depth beyond the depth of the deep source portion.

4. The method of claim 1 wherein the deep source portion is formed using a sloping implant.

5. The method of claim 3, wherein the deep body portion is formed using a sloping implant.

6. The method of claim 4 wherein the sloping implant is formed on two quadrants.

7. The method of claim 5 wherein the sloping implant is formed on two quadrants.

8. An insulated trench-gate power device comprising:

a semiconductor substrate;

a body region in the semiconductor substrate;

a surface source region on the body region;

a trench-gate structure for forming a gate region of the device including a trench made in the semiconductor substrate; and

wherein the surface source region includes a deep source portion along the trench.

9. The device of claim 8, wherein the body region comprises a deep body portion along the trench.

10. The device of claim 9, wherein the deep body portion extends to a predetermined depth beyond the depth of the deep source portion.

11. An insulated trench-gate device comprising:

an insulated trench;

a source region adjacent to the insulated trench; and

a deep source region along the insulated trench, wherein the channel length of the device is determined independently from the thermal budget of the device.

12. The insulated trench gate device of claim 11 wherein the channel length of the device is also determined independently from the dopant used for forming the source region.

13. The insulated trench gate device of claim 11 wherein the insulated trench comprises a trench having a U-shaped profile.

14. The insulated trench gate device of claim 11 wherein the insulated trench further comprises a recessed polysilicon portion.

15. The insulated trench gate device of claim 14 wherein the thermal processes used to form the source and the etching process used to recess the polysilicon portion are independent.

16. The insulated trench gate device of claim 11 wherein the trench further comprises a thick oxide portion.

17. The insulated trench gate device of claim 11 further comprising a deep body portion.

18. The insulated trench gate device of claim 17 wherein the depth of the deep body portion extends below the depth of the deep source region.

19. The insulated trench gate device of claim 11 further comprising a body region.

20. The insulated trench gate device of claim 11 wherein the trench further comprises a recessed portion.