Semiconductor device with modified mobility and thin film transistor having the same

• US 20050139923A1
• Filed: 12/28/2004
• Published: 06/30/2005
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Young-soo, Kwon, Jang-yeon, Noguchi, Takashi, Kim, Do-young
• Granted Patent: US 7,479,667 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02678 Beam shaping, e.g. using a mask
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1296 adapted to increase the uniformity of device parameters
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided are a semiconductor device including an active area which is defined as high and low mobility areas and a thin film transistor having the semiconductor device. The mobility of the active area can be lowered to a level enough to satisfy the requirement of the semiconductor device. The lowering of the mobility of the active area can contribute to reducing mobility deviation between semiconductor devices. As a result, the quality of a flat panel display adopting a large-scale semiconductor device can be greatly improved.

Claims

1. A semiconductor device comprising a silicon-based active area comprising high and low mobility areas over an electron mobility path.

2. The semiconductor device of claim 1, wherein a plurality of at least one of the high and low mobility areas are provided.

3. The semiconductor device of claim 1, wherein the low mobility area is formed in the center of the high mobility area.

4. The semiconductor device of claim 1, wherein the high mobility area has a polycrystalline structure, and the low mobility area has an amorphous structure.

5. The semiconductor device of claim 1, wherein the high mobility area has a polycrystalline structure, and the low mobility area has a micro polycrystalline structure.

6. The semiconductor device of claim 1, wherein the high mobility area has a SiGe crystalline structure, and the low mobility area has a single crystalline structure.

7. A thin film transistor comprising:

a Si-based channel;

source and drain which are formed beside respective sides of the Si-based channel;

a gate which applies an electric field to the Si-based channel; and

an insulating layer which is interposed between the active area and the gate,

wherein the Si-based channel comprises high and low mobility areas over an electron mobility path.

8. The thin film transistor of claim 7, wherein a plurality of at least one of the high and low mobility areas are provided.

9. The thin film transistor of claim 7, wherein the low mobility area is formed in the center of the high mobility area.

10. The thin film transistor of claim 7, wherein the high mobility area has a polycrystalline structure, and the low mobility area has an amorphous structure.

11. The thin film transistor of claim 7, wherein the high mobility area has a polycrystalline structure, and the low mobility area has a micro polycrystalline structure.

12. The thin film transistor of claim 7, wherein the high mobility area has a SiGe crystalline structure, and the low mobility area has a single crystalline structure.