Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

• US 20050139959A1
• Filed: 02/28/2005
• Published: 06/30/2005
• Est. Priority Date: 06/11/1999
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ning, Tak H., Cote, William J., Bernstein, Kerry, Bracchitta, John A., Pricer, Wilbur D.
• Granted Patent: US 7,195,971 B2
• Time in Patent Office: Days
• US Class Current: 257/595
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Claims

1-16. -16. (canceled)

17. A method of manufacturing a capacitor, the method comprising:

forming interdigitized metal wires on a first low dielectric material;

depositing a high dielectric material between each of said interdigitized metal wires; and

depositing a second low dielectric material on said high dielectric material such that said interdigitized metal wires are provided between said first and second low dielectric material.

18. The method of claim 17, further comprising depositing polish stop material at least on said metal wires prior to depositing said high dielectric material.

19. The method of claim 17, wherein said polish stop is also deposited on said first low dielectric material between said interdigitized metal wires.

20. The method of claim 19, further comprising etching back said high dielectric material at least to a top surface of said interdigitized metal wires.

21. A method of manufacturing a capacitor, the method comprising:

depositing high dielectric material on a first low dielectric material;

etching a trough region in said high dielectric material;

filing said trough region with metal; and

depositing second low dielectric material on said trough region filled with said metal and said high dielectric material.

22. The method of claim 21, further comprising depositing an etch stop layer on said first low dielectric material such that said etch stop layer is between said high dielectric material and said first low dielectric material.

23. The method of claim 22, further comprising removing said etch stop layer from areas within said trough region after etching said trough and prior to filling said trough region with said metal.

24-39. -39. (canceled)