Semiconductor chip package and multichip package

• US 20050139985A1
• Filed: 05/11/2004
• Published: 06/30/2005
• Est. Priority Date: 12/25/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Inventors: Takahashi, Norio
• Granted Patent: US 7,576,431 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48235 connecting the wire to a via metallisation of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

The present invention provides a multichip package wherein a plurality of semiconductor chip packages (100) in each of which first electrode pads (16a) provided in a main surface of a semiconductor chip, and first bonding pads (20a) and first central bonding pads (18a) formed in an upper area of the main surface are respectively electrically connected by first redistribution wiring layers (24) in a one-to-one correspondence relationship, and second electrode pads (17b), and second bonding pads (22b) and second central bonding pads (18b) formed in an upper area of the main surface are respectively electrically connected by second redistribution wiring layers (26) in a one-to-one correspondence relationship, are stacked on one another.

Claims

1. A semiconductor chip package, comprising:

a semiconductor chip having a rectangular main surface, wherein the rectangular main surface has a first side and a second side opposite to the first side;

a plurality of first electrode pads which is provided on the main surface along the first side;

a plurality of second electrode pads which is provided on the main surface along the second side;

a plurality of central bonding pads which is provided between the first electrode pads and the second electrode pads on the main surface, wherein the central bonding pads are located near the first electrode pads;

a plurality of first bonding pads which is provided between the first side and the first electrode pads on the main surface, wherein the first bonding pads are provided along the first side;

a plurality of second bonding pads which is provided between the second side and the second electrode pads on the main surface, wherein the second bonding pads are provided along the second side;

a plurality of first redistribution wiring layers which electrically connects the first electrode pads, the first central bonding pads and the first bonding pads in a one-to-one correspondence relationship, respectively;

a plurality of second redistribution wiring layers which electrically connects the second electrode pads, the second central bonding pads and the second bonding pads in a one-to-one correspondence relationship, respectively; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second central bonding pads and top faces of the first and second bonding pads to be exposed.

2. A semiconductor chip package according to claim 1, wherein the first central bonding pads and the second central bonding pads are alternately disposed in alignment.

3. A multichip package, comprising:

a plurality of semiconductor chip packages each including;

a semiconductor chip having a rectangular main surface;

a first electrode pad group provided on the main surface in parallel along a first side defining the main surface, said first electrode pad group including a plurality of first electrode pads;

a second electrode pad group provided on the main surface in parallel along a second side defining the main surface and opposite to the first side, said second electrode pad group including a plurality of second electrode pads;

a central bonding pad group provided parallel to the first electrode pad group, in an area of the main surface, lying between the first and second electrode pad groups and at positions near the first electrode pad group, said central bonding pad group including a plurality of first central bonding pads respectively corresponding to the first electrode pads and a plurality of second central bonding pads respectively corresponding to the second electrode pads;

a first bonding pad group provided in an area of the main surface, which is placed between the first electrode pad group and the first side, said first bonding pad group including a plurality of first bonding pads respectively provided corresponding to the first electrode pads in parallel with the first side;

a second bonding pad group provided in an area of the main surface, which is placed between the second electrode pad group and the second side, said second bonding pad group including a plurality of second bonding pads respectively provided corresponding to the second electrode pads in parallel with the second side;

first redistribution wiring layers that electrically connect the first electrode pads, the first central bonding pads and the first bonding pads in a one-to-one correspondence relationship, respectively;

second redistribution wiring layers that electrically connect the second electrode pads, the second central bonding pads and the second bonding pads in a one-to-one correspondence relationship, respectively; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second central bonding pads and top faces of the first and second bonding pads to be exposed.

wherein the plurality of semiconductor chip packages are stacked on one another with being shifted in their thickness direction.

4. A multichip package according to claim 3, wherein the plurality of semiconductor chip packages are laminated in such a manner that the main surfaces thereof are faced in the same direction, and side faces thereof including the first sides thereof are faced in the same direction, and the semiconductor chip packages are respectively laminated in the direction from the first sides to the second sides such that the central bonding pad groups included in the semiconductor chip packages are exposed.

6. A multichip package according to claim 3, further including:

a substrate equipped with a laminated body in which a plurality of the semiconductor chip packages are laminated in their thickness direction,

wherein the substrate has an opposite area opposite to the laminated body and first and second non-opposite areas provided at positions where the opposite area is interposed therebetween as viewed in the direction normal to the first and second sides, and third bonding pads are formed on the surface of the first non-opposite area and fourth bonding pads are formed on the surface of the second non-opposite area,

wherein the third bonding pads and the first boding pads of the semiconductor chip package brought into contact with the substrate are electrically connected by first bonding wires respectively,

wherein the first central bonding pads of the laminated semiconductor chip package on the lower side and the first bonding pads of the semiconductor chip package on the upper side are electrically connected by second boding wires respectively,

wherein the second central boding pads of the semiconductor chip package farthest away from the substrate and the second central bonding pads of the lower semiconductor chip package brought into contact with the farthest semiconductor chip package are electrically connected by third bonding wires respectively, and

wherein the second bonding pads of the semiconductor chip package farthest away from the substrate and the fourth boding pads are electrically connected by fourth bonding wires respectively.

5. A multichip package, comprising:

a plurality of semiconductor chip packages each including;

a semiconductor chip having a rectangular main surface;

a first electrode pad group provided on the main surface in parallel along a first side defining the main surface, said first electrode pad group including a plurality of first electrode pads;

a second electrode pad group provided on the main surface in parallel along a second side defining the main surface and opposite to the first side, said second electrode pad group including a plurality of second electrode pads;

a central bonding pad group provided parallel to the first electrode pad group, in an area of the main surface, lying between the first and second electrode pad groups and at positions near the first electrode pad group, said central bonding pad group including a plurality of first central bonding pads respectively corresponding to the first electrode pads and a plurality of second central bonding pads respectively corresponding to the second electrode pads;

a first bonding pad group provided in an area of the main surface, which is placed between the first electrode pad group and the first side, said first bonding pad group including a plurality of first bonding pads respectively provided corresponding to the first electrode pads in parallel with the first side;

a second bonding pad group provided in an area of the main surface, which is placed between the second electrode pad group and the second side, said second bonding pad group including a plurality of second bonding pads respectively provided corresponding to the second electrode pads in parallel with the second side;

first redistribution wiring layers that electrically connect the first electrode pads, the first central bonding pads and the first bonding pads in a one-to-one correspondence relationship, respectively;

second redistribution wiring layers that electrically connect the second electrode pads, the second central bonding pads and the second bonding pads in a one-to-one correspondence relationship, respectively; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second central bonding pads and top faces of the first and second bonding pads to be exposed.

wherein the plurality of semiconductor chip packages are stacked on one another in their thickness direction, the main surfaces of the respective semiconductor chip packages are faced in the same direction and side faces thereof including the first faces thereof are faced in the same direction, and the semiconductor chip packages are respectively laminated with being shifted from one another in the direction from the first sides to the second sides in such a manner that the central bonding pad groups included in the semiconductor chip packages are exposed.

7. A multichip package, comprising:

a semiconductor chip having a first rectangular main surface;

a semiconductor chip package having a second rectangular main surface and an encapsulation layer for covering the second main surface, wherein the semiconductor chip package is located on the first rectangular main surface of the semiconductor chip with being shifted in its thickness direction.

8. A multichip package according to claim 7, wherein parts of both the first main surface of the semiconductor chip and the second main surface of the semiconductor chip package are respectively laminated so as to be exposed.

9. A multichip package according to claim 7, wherein the same positions of both the first main surface of the semiconductor chip and the second main surface of the semiconductor chip package are respectively laminated so as to be exposed.

10. A multichip package, comprising:

a substrate having a first main surface and having, on the first main surface, a first area in which substrate bonding pads are provided, and a second area adjacent to the first area;

at least one semiconductor chip having a rectangular second main surface and a back surface opposite to the second main surface, which is placed on the second area, said semiconductor chip including a third area in which a plurality of semiconductor chip bonding pads respectively electrically connected to the substrate bonding pads are provided in the neighborhood of a side of the second main surface, closest to the substrate bonding pads, and a fourth area adjacent to the third area; and

at least one semiconductor chip package having a rectangular third main surface and a back surface opposite to the third main surface, which is placed on the fourth area, said third main surface being provided thereon with first and second semiconductor chip package bonding pads respectively electrically connected to the semiconductor chip bonding pads, said semiconductor chip package including redistribution wring layers that respectively electrically connect the first and second semiconductor chip package bonding pads, and an encapsulating layer that covers the third main surface so as to expose top faces of the first and second semiconductor chip package bonding pads respectively.

11. A multichip package, comprising:

a substrate having a first main surface and having, on the first main surface, a first area in which first substrate bonding pads are provided, a second area in which second substrate bonding pads are provided, and a third area provided at a position where the third area is interposed between the first and second areas; and

a laminated body in which a plurality of semiconductor chip packages each having a rectangular second main surface and including a plurality of first semiconductor chip package bonding pads provided in the neighborhood of a first side defining the second main surface, and second semiconductor chip package bonding pads which are provided in the neighborhood of a second side opposite to the first side defining the second main surface and respectively electrically connected to the first semiconductor chip package bonding pads are laminated with being shifted in their thickness direction such that the first semiconductor chip package bonding pads are exposed;

wherein the laminated body is mounted on the third area of the substrate,

wherein the first substrate bonding pads and the first semiconductor chip package bonding pads of the semiconductor chip package brought into contact with the substrate are respectively electrically connected by first bonding wires,

wherein the first semiconductor chip package bonding pads of the laminated semiconductor chip package on the lower side, and the first semiconductor chip package bonding pads of the semiconductor chip package on the upper side are respectively electrically connected by second bonding wires, and

wherein the second semiconductor chip package bonding pads of the semiconductor chip package farthest away from the substrate, and the second substrate bonding pads are respectively electrically connected by third bonding wires.

12. A multichip package, comprising:

a pair of semiconductor chip structural bodies each including,

a semiconductor chip having a rectangular main surface;

a first electrode pad group provided on the main surface, said first electrode pad group including a plurality of first electrode pads provided in parallel along a first side defining the main surface and provided in order from the 1st to n (where n;

integer greater than or equal to

     2)th first electrode pads; and

a second electrode pad group provided on the main surface, said second electrode pad group including a plurality of second electrode pads provided in parallel along a second side defining the main surface and opposite to the first side and provided in order from the 1st to n (where n;

integer greater than or equal to

     2)th second electrode pads,

wherein one of the pair of semiconductor chip structural bodies is configured as a semiconductor chip package, said one further including;

a first bonding pad group including, in an area between the first electrode pad group and the first side, of the main surface, first bonding pads provided in reverse order from the n (where n;

integer greater than or equal to

     2)th to 1st first bonding pads, corresponding to the first electrode pads in parallel to the first side;

a second bonding pad group including, in an area between the second electrode pad group and the second side, of the main surface, second bonding pads provided in reverse order from the n (where n;

integer greater than or equal to

     2)th to 1st second bonding pads, corresponding to the second electrode pads in parallel to the second side;

first redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th first electrode pads and the i (where i;

integers from 1 to n)th first bonding pads;

second redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th second electrode pads and the i (where i;

integers from 1 to n)th second bonding pads; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second bonding pads to be exposed respectively,

wherein the pair of semiconductor chip structural bodies are stacked on one another in such a manner that the back surfaces of the semiconductor chips respectively included in the semiconductor chip structural bodies are faced each other and side faces of the semiconductor chips, containing the first sides thereof are faced in the same direction.

13. A multichip package according to claim 12, further including:

a plurality of conductive portions which are respectively provided at positions opposite to the side faces on the respective sides of the first and second sides, of the pair of semiconductor chip structural bodies when the pair of semiconductor chip structural bodies are seen from above on a plane basis, and which extend in the direction normal to the first and second sides,

wherein the i (where i;

integers from 1 to n)th first bonding pads on the one semiconductor chip structural body side, and the i (where i;

integers from 1 to n)th first electrode pads on the other semiconductor chip structural body side are respectively electrically connected to the same conductive portions by first bonding wires,

wherein the i (where i;

integers from 1 to n)th second bonding pads on the one semiconductor chip structural body side, and the i (where i;

integers from 1 to n)th second electrode pads on the other semiconductor chip structural body side are respectively electrically connected to the same conductive portions by second bonding wires.

14. A multichip package, comprising:

semiconductor chip structural bodies provided in pair, said semiconductor chip structural body including a semiconductor chip having a rectangular main surface, and being provided on the main surface and having a first electrode pad group including a plurality of first electrode pads provided in order from the 1st to n (where n;

integer greater than or equal to

     2)th first electrode pads, and a second electrode pad group including the 1st to n (where n;

integer greater than or equal to

     2)th second electrode pads,

wherein the first electrode pad group is provided on the side of the first side along a virtual line lying between first and second sides defining the main surface and opposite to each other and extending in parallel to these sides, and the second electrode pad group is provided on the side of the second side,

wherein one of the pair of semiconductor chip structural bodies is configured as a semiconductor chip package, said one further including;

a first bonding pad group including, in an area between the first electrode pad group and the first side, of the main surface, a plurality of bonding pads provided in order from the 1st to n (where n;

integer greater than or equal to

     2)th first bonding pads, corresponding to the first electrode pads in parallel to the first side;

a second bonding pad group including, in an area between the second electrode pad group and the second side, of the main surface, a plurality of second bonding pads provided in order from the 1st to n (where n;

integer greater than or equal to

     2)th second bonding pads, corresponding to the second electrode pads in parallel to the second side;

first redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th first electrode pads and the i (where i;

integers from 1 to n)th first bonding pads;

second redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th second electrode pads and the i (where i;

integers from 1 to n)th second bonding pads; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second bonding pads to be exposed respectively,

wherein the other of the pair of semiconductor chip structural bodies is configured as a semiconductor chip package, said the other further including;

a first bonding pad group including, in an area between the first electrode pad group and the first side, of the main surface, first bonding pads provided in reverse order from the n (where n;

integer greater than or equal to

     2)th to 1st first bonding pads, corresponding to the first electrode pads in parallel to the first side;

a second bonding pad group including, in an area between the second electrode pad group and the second side, of the main surface, second bonding pads provided in reverse order from the n (where n;

integer greater than or equal to

     2)th to 1st second bonding pads, corresponding to the second electrode pads in parallel to the second side;

first redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th first electrode pads and the i (where i;

integers from 1 to n)th first bonding pads;

second redistribution wiring layers that respectively electrically connect the i (where i;

integers from 1 to n)th second electrode pads and the i (where i;

integers from 1 to n)th second bonding pads; and

an encapsulating layer formed on the main surface with a thickness that causes top faces of the first and second bonding pads to be exposed respectively,

wherein the pair of semiconductor chip structural bodies are stacked on one another in such a manner that the back surfaces of the semiconductor chips respectively included in the semiconductor chip structural bodies are faced each other and side faces of the semiconductor chips, containing the first sides thereof are faced in the same direction.

15. A multichip package according to claim 14, wherein the virtual line is set as a center line in which the distances from the first side and the second side are equal to each other.

16. A multichip package according to claim 14, wherein a plurality of conductive portions which are respectively provided at positions opposite to the side faces on the respective sides of the first and second sides, of the pair of semiconductor chip structural bodies when the pair of semiconductor chip structural bodies are seen from above on a plane basis, and which extend in the direction normal to the first and second sides,

wherein the i (where i:

integers from 1 to n)th first bonding pads on the one semiconductor chip structural body side, and the i (where i;

integers from 1 to n)th first electrode pads on the other semiconductor chip structural body side are respectively electrically connected to the same conductive portions by first bonding wires,

wherein the i (where i;

integers from 1 to n)th second bonding pads on the one semiconductor chip structural body side, and the i (where i;

integers from 1 to n)th second electrode pads on the other semiconductor chip structural body side are respectively electrically connected to the same conductive portions by second bonding wires.