Probe card with coplanar daughter card

• US 20050140381A1
• Filed: 02/15/2005
• Published: 06/30/2005
• Est. Priority Date: 04/10/2001
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Sporck, A. Nicholas, Shinde, Makarand S.
• Granted Patent: US 7,116,119 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 1/07342 the body of the probe being at an angle other than perpendicular to test object, e.g. probe card

Abstract

A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to be input into the semiconductor and/or response signals generated by the semiconductor device in response to the test signals.

Claims

1-57. -57. (canceled)

58. A method of testing a semiconductor device, said method comprising:

receiving at a substrate test signals from a semiconductor tester apparatus;

enhancing said test signals using an electric circuit that is disposed at least in part on a daughter card attached to a first side of said substrate; and

outputting said enhanced test signals to said semiconductor device through probes that are disposed to a second side of said substrate, wherein said second side of said substrate is opposite said first side.

59. The method of claim 58, wherein said electric circuit comprises at least one of a digital logic element, a microprocessor, an analog circuit element, a digital-to-analog converter, or an analog-to-digital converter.

60. The method of claim 58, wherein said electric circuit enhances said test data by customizing at least a portion of said test data to test needs of said semiconductor device under test.

61. The method of claim 60, wherein said test data comprises test signals generated by said semiconductor test apparatus and said electric circuit customizes at least a portion of said test signals.

62. The method of claim 60, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.

63. The method of claim 58 further comprising a plurality of said daughter cards.

64. The method of claim 63, wherein said plurality of daughter cards are disposed in stacked relationship to each other.

65. The method of claim 63, wherein at least a portion of said electric circuit is disposed on each of said plurality of daughter cards.

66. The method of claim 65, wherein said electric circuit comprises at least one of a digital logic element, a microprocessor, an analog circuit element, a digital-to-analog converter, or an analog-to-digital converter.

67. The method of claim 65, wherein said electric circuit enhances said test data by customizing at least a portion of said test data to test needs of said semiconductor device under test.

68. The method of claim 67, wherein said test data comprises test signals generated by said semiconductor test apparatus and said electric circuit customizes at least a portion of said test signals.

69. The method of claim 67, wherein said test data comprises response signals generated by said semiconductor device under test and said electric circuit customizes at least a portion of said response signals.

70. The method of claim 63, wherein said plurality of daughter cards includes at least three daughter cards.

71. The method of claim 70, wherein at least a portion of said electric circuit is disposed on each of said at least three daughter cards.

72. The method of claim 70, wherein said at least three daughter cards are disposed in stacked relationship to each other.

73. A method for electrically communicating test data between a semiconductor test apparatus and a semiconductor device under test, said method comprising:

configuring a printed circuit board to electrically contact said semiconductor tester apparatus,

configuring a plurality of probes to electrically contact said semiconductor device,

providing a daughter card on said printed circuit board, and

configuring an electric circuit to receive as input test data received at said probe card assembly from one of said tester apparatus or said semiconductor device under test, enhance said test data, and output enhanced test data, at least a portion of said electric circuit being disposed on said daughter card.

74. The method of claim 73 further comprising providing a plurality of said daughter cards.

75. The method of claim 74, wherein said daughter cards are disposed in stacked relationship to each other.

76. The method of claim 74, wherein said plurality of daughter cards includes at least two daughter cards.

77. The method of claim 74, wherein said plurality of daughter cards includes at least three daughter cards.

78. The method of claim 73, wherein said test data comprises test signals generated by said semiconductor tester apparatus and said electric circuit processes at least a portion of said test signals.

79. The method of claim 73, wherein said test data comprises response signals generated by said semiconductor device and said electric circuit processes at least a portion of said response signals.

80. The method of claim 73, wherein said plurality of probes are configured to contact a plurality of semiconductor devices under test, and said electric circuit enhances said test data by receiving test signals from said semiconductor tester apparatus for testing a first number of semiconductor devices and outputting to said probes test signals for testing a second number of semiconductor devices, wherein said second number is greater than said first number.

81. The method of claim 73, wherein said daughter card is secured substantially coplanar to said substrate and there is a space between said daughter card and said substrate.