SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER WITH SAMPLE AND HOLD ELEMENT

• US 20050140538A1
• Filed: 12/31/2003
• Published: 06/30/2005
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: A, Chandra Shekar
• Granted Patent: US 6,906,657 B1
• Time in Patent Office: Days
• US Class Current: 341/163
• CPC Class Codes: H03M 1/40 recirculation type

Abstract

According to some embodiments, a successive approximation analog-to-digital converter is provided.

Claims

1. An apparatus, comprising:

a comparator to receive an analog input signal V_IN along with a comparison signal V_C and to generate a digital result, the comparison signal V_C being received at a comparison node;

a higher-threshold sample and hold element to receive V_C and to selectively provide V_H to a higher-threshold node;

a hither-threshold resistor having a resistance R coupled between the higher-threshold node and the comparison node;

a lower-threshold sample and hold element to receive V_C and to selectively provide V_L to a lower-threshold node; and

a lower-threshold resistor coupled between the lower-threshold node and the comparison node.

2. The apparatus of claim 1, wherein

the comparison signal is adjusted based on successive digital results from the comparator and V_C substantially equals (V_H+V_L)/2.

3. The apparatus of claim 1, wherein the lower-threshold resistor has a resistance substantially equal to R.

4. The apparatus of claim 1, wherein the higher-threshold and lower-threshold sample and hold elements are amplifiers each having an output that is isolated from an input.

5. The apparatus of claim 1, further comprising:

a first switch coupled between the higher-threshold node and a reference voltage; and

a second switch coupled between the lower-threshold node and ground.

6. The apparatus of claim 5, wherein the first and second switches are to be closed to initialize V_H to the reference voltage and V_L to ground.

7. The apparatus of claim 5, further comprising:

a third switch coupled between the output of the higher-threshold sample and hold element and the higher-threshold node; and

a fourth switch coupled between the output of the lower-threshold sample and hold element and the lower-threshold node.

8. The apparatus of claim 1, further comprising:

a multi-bit result register to store results from the comparator.

9. The apparatus of claim 1, wherein the apparatus is further to convert multiple digital input signals into an analog output signal V_OUT.

10. A method, comprising:

initially setting a higher-threshold signal V_H;

comparing an analog input signal V_IN to a comparison signal V_C;

providing a digital result of the comparison;

when a digital result indicates V_IN is less than the existing V_C transferring the existing V_C through a sample and hold element to set V_H to the existing V_C; and

successively performing comparisons and transfers to generate a digital representation of V_IN.

11. The method of claim 10, further comprising:

initially setting a lower-threshold signal V_L, wherein V_C substantially equals (V_H+V_L)/2.

14. The method of claim 11, further comprising:

when a digital result indicates V_IN is not less than the existing V_C, setting V_L to the existing V_C.

16. The method of claim 11, wherein V_H is initially set to a reference voltage and V_L is initially set to ground.

17. The method of claim 10, wherein said providing comprising:

storing results in a multi-bit result register.

12-13. -13. (canceled)

15. The method of claim 15, wherein V_L is set to the existing V_C by transferring the existing V_C through a sample and hold element.

18. A system, comprising:

a processor having an analog to digital conversion portion that includes;

a comparator to receive an analog input signal V₁ along with a comparison signal V_C and to generate a digital result, the comparison sip-nal V_C being received at a comparison node,

a higher-threshold sample and hold element to receive V_C and to selectively provide V_H to a higher-threshold node,

a hither-threshold resistor having a resistance R coupled between the higher-threshold node and the comparison node,

a lower-threshold sample and hold element to receive V_C and to selectively provide V_L to a lower-threshold node, and

a lower-threshold resistor coupled between the lower-threshold node and the comparison node; and

a battery input to receive power to be provided to the processor.

19. The system of claim 18, wherein:

the comparison signal is adjusted based on successive digital results from the comparator and V_C substantially equals (V_H+V_L)/2.

20. The system of claim 19, wherein the lower-threshold resistor has a resistance substantially equal to R.