Semiconductor memory device

• US 20050141260A1
• Filed: 03/07/2005
• Published: 06/30/2005
• Est. Priority Date: 02/27/2003
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Hideaki
• Granted Patent: US 7,280,384 B2
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

In a semiconductor memory device including memory cells respective having a ferroelectric capacitor, and are provided at intersection portions of sets of a plurality of word lines and plate lines which is adjacent thereto, with bit lines, clamp circuits are respectively connected between the bit lines and nodes being supplied with reference potentials. Herewith, electric charges supplied from the ferroelectric capacitors to the bit lines are extracted by the clamp circuits, and capacities of the bit lines are increased artificially. Consequently, during a data read operation, an amount of electric potential change of the bit lines according to stored data in the ferroelectric capacitors is improved, and it becomes possible to obtain a large potential difference between the bit lines.

Claims

1. A semiconductor memory device, comprising:

a plurality of word lines;

plate lines respectively provided to adjacent to said word lines;

a plurality of bit lines provided in an orthogonal direction relative to said word lines and said plate lines;

memory cells provided at intersection portions of sets of said word lines and said plate lines, with said bit lines, and respective having a ferroelectric capacitor; and

clamp circuits respectively connected between said bit lines and nodes being supplied with reference potentials.

2. The semiconductor memory device according to claim 1;

wherein said memory cell each has one transistor and one ferroelectric capacitor.

3. The semiconductor memory device according to claim 1;

wherein said memory cell each has two transistors and two ferroelectric capacitors, and is provided at an intersection portion of a set of said word line and said plate line, with a pair of said bit lines.

4. The semiconductor memory device according to claim 1;

wherein said clamp circuit is a resistor of which one end is connected to said bit line and the other end is connected to the node being supplied with the reference potential.

5. The semiconductor memory device according to claim 1;

wherein said clamp circuit has a switching function controlling whether between said bit line and the node being supplied with the reference potential is electrically connected or not.

6. The semiconductor memory device according to claim 5;

wherein said clamp circuit is a transistor whose ON resistance is larger than that of the transistor constituting said memory cell, in which a drain is connected to said bit line, a source is connected to the node being supplied with the reference potential, and a gate is connected to a control signal line.

7. The semiconductor memory device according to claim 5;

wherein said clamp circuit has a transistor in which a drain is connected to said bit line, and a gate is connected to the control signal line, and a resistor in which one end is connected to a source of the corresponding transistor and the other end is connected to the node being supplied with the reference potential.

8. The semiconductor memory device according to claim 5;

wherein said clamp circuit insulates between said bit line and the node being supplied with the reference potential when a sense amplifier amplifying a potential difference between said bit lines is active.

9. The semiconductor memory device according to claim 5;

wherein said clamp circuit insulates between said bit line and the node being supplied with the reference potential during a data write operation.

10. The semiconductor memory device according to claim 5;

wherein said clamp circuit insulates between said bit line and the node being supplied with the reference potential when the sense amplifier amplifying the potential difference between said bit lines is active and during the data write operation.

11. The semiconductor memory device according to claim 1;

wherein the reference potential is a ground level.

12. The semiconductor memory device according to claim 1;

wherein said clamp circuits respectively have a plurality of clamp elements, and the plurality of clamp elements are connected to intersect between the clamp circuits corresponding to a pair of bit lines.

13. The semiconductor memory device according to claim 1;

wherein said clamp circuits respectively have two clamp elements, and a first clamp element of a first clamp circuit and a second clamp element of a second clamp circuit are connected, and a first clamp element of the second clamp circuit and a second clamp element of the first clamp circuit are connected in the first clamp circuit and the second clamp circuit respectively connected to a pair of bit lines.

14. The semiconductor memory device according to claim 1;

wherein said clamp circuit is a constant current source circuit.