Semiconductor device

• US 20050141266A1
• Filed: 12/28/2004
• Published: 06/30/2005
• Est. Priority Date: 12/31/2003
• Status: Abandoned Application

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: Dongbuanam Semiconductor, Inc. (DB HiTek Co., Ltd.)
• Inventors: Jung, Jin Hyo
• Application Number:
  US11/022,684
• Publication Number:
  US 20050141266A1
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence

Abstract

An nvSRAM having a stacked oxide layer is disclosed. A disclosed device comprises: two NMOS transistors and two PMOS transistors for an SRAM latch; two NMOS pass gates for reading and writing a HIGH condition and a LOW condition that are formed in the SRAM latch; and two floating gate NVM devices of split gate structure for storing the HIGH condition and the LOW condition that are stored in the SRAM latch when the power is off.

Claims

1. A semiconductor device comprising:

two NMOS transistors and two PMOS transistors for an SRAM latch;

two NMOS pass gates for reading and writing a HIGH condition and a LOW condition that are formed in the SRAM latch; and

two floating gate NVM devices of split gate structure for storing the HIGH condition and the LOW condition that are stored in the SRAM latch when the power is off.

2. A semiconductor device as defined by claim 1, wherein a bias voltage is applied to the well region where the floating gate NVM device of split gate structure is positioned.

3. A semiconductor device as defined by claim 1, wherein the well regions on which the SRAM latch and the floating gate NVM device of split gate structure are positioned are isolated from each other by a deep well of the conductive type opposite to them.

4. A semiconductor device as defined by claim 1, wherein the floating gate NVM device of split gate structure comprises a stacked structure having a tunnel oxide layer, a floating gate, an ONO layer and a control gate, a split gate on the sidewalls of the stacked structure, an insulation layer between the stacked structure and the split gate, and drain and source regions located under the sidewalls of the stacked structure and the split gate.

5. A semiconductor device comprising:

a semiconductor substrate of the first conductive type;

a MOS transistor of the first conductive type including a first well of the second conductive type in the semiconductor substrate a gate on the first well of the second conductive type and impurity regions of the first conductive type under the sidewalls of the gate;

a MOS transistor of the second conductive type including a first well of the first conductive type in the substrate neighboring a device isolation structure next to the first well of the second conductive type, a gate on the first well of the first conductive type and impurity regions of the second conductive type under the sidewalls of the gate;

a second well of the first conductive type in the substrate neighboring a device isolation structure next to the first well of the first conductive type;

a second well of the second conductive type under the second well of the first conductive type;

a floating gate NVM device of split gate structure on the second well of the first conductive type, and source and drain regions of the second conductive type in the second well of the first conductive type; and

an impurity region of the first conductive type in the second well of the first conductive type.

6. A semiconductor device as defined by claim 5, wherein the impurity region of the first conductive type is isolated from the drain region of the floating gate NVM device of split gate structure by a device isolation structure.

7. A semiconductor device as defined by claim 5, wherein the second well of the second conductive type isolates the first well of the first conductive type from the second well of the first conductive type.