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Semiconductor device

  • US 20050141266A1
  • Filed: 12/28/2004
  • Published: 06/30/2005
  • Est. Priority Date: 12/31/2003
  • Status: Abandoned Application
First Claim
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1. A semiconductor device comprising:

  • two NMOS transistors and two PMOS transistors for an SRAM latch;

    two NMOS pass gates for reading and writing a HIGH condition and a LOW condition that are formed in the SRAM latch; and

    two floating gate NVM devices of split gate structure for storing the HIGH condition and the LOW condition that are stored in the SRAM latch when the power is off.

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