Method of manufacturing a semiconductor integrated circuit device

• US 20050142713A1
• Filed: 08/18/2004
• Published: 06/30/2005
• Est. Priority Date: 10/17/2002
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto, Salama, C. Andre T.
• Granted Patent: US 7,344,935 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of manufacturing a semiconductor integrated circuit (IC) device that integrates a TLPM and one or more planar semiconductor devices on a semiconductor substrate. In manufacturing the semiconductor IC device according to one embodiment, a trench etching forms a trench. A p-type body region, an n-type expanded drain region, and a thick oxide film are formed. A second trench etching deepens the trench. Gate oxide films and gate electrodes of the TLPM, an NMOSFET, and a PMOSFET are formed. P-type base regions of the TLPM and an NPN bipolar transistor are formed. An n-type source and drain region of the TLPM, and n-type diffusion regions of the NMOSFET and the NPN bipolar transistor are formed. P-type diffusion regions of the PMOSFET and the NPN bipolar transistor are formed. An interlayer oxide film, a contact electrode, and constituent metal electrodes are formed.

Claims

1. A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate, a planar MOSFET exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising:

forming one or more well regions of a first conductivity type and one or more well regions of a second conductivity type in a surface of the semiconductor substrate;

forming an oxide film on the surface of the semiconductor substrate to form a mask;

forming a trench, using the oxide mask, in one of the well regions of the second conductivity type for forming the trench lateral MOSFET;

forming an expanded drain region of the second conductivity type around the trench;

forming a thick oxide film on an inner side wall of the trench;

etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask;

removing the oxide film on the surface of the semiconductor substrate;

forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed;

forming a selective oxide film using the nitride mask;

forming gate oxide films inside the trench and on the surface of one of the well regions of the first conductivity type for forming the planar MOSFET;

forming gate electrodes on the respective gate oxide films;

forming a base region of the first conductivity type in the bottom of the trench;

forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, forming a drain region of the second conductivity type outside an upper portion of the trench, and forming diffusion regions of the second conductivity type selectively in the well region of the first conductivity type for forming the planar MOSFET, one of the diffusion regions operating as a source or a drain of the planar MOSFET and the other one of the diffusion regions operatng as a drain or a source of the planar MOSFET;

forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench;

removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region;

filling the trench with a contact electrode; and

forming a metal electrode connected to the contact electrode, forming metal electrodes connected to the respective gate electrodes, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.

5. The method of claims 1, 2, 3, or 4, wherein the oxide film on the surface of the substrate is removed by dry etching after the bottom of the trench is etched.

6. The method of claims 1, 2, 3, or 4, wherein the oxide film on the surface of the substrate is removed by wet etching after the bottom of the trench is etched.

7. The method of claims 1, 2, 3, or 4, wherein the part of the nitride film operating as a mask for forming the selective oxide film is removed by dry etching.

8. The method of claims 1, 2, 3, or 4, wherein the part of the nitride film operating as a mask for forming the selective oxide film is removed by wet etching using a phosphoric etchant.

10. The method of claims 1, 2, 3, or 4, wherein the portion of the interlayer insulation film on the surface of the semiconductor substrate is thicker than the portion of the interlayer insulation film inside the trench, and the interlayer insulation film is etched by anisotropic etching to remove the portion of the interlayer insulation film in the bottom of the trench.

2. A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate, a planar MOSFET exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising:

forming two or more well regions of a second conductivity type in a surface of the semiconductor substrate;

forming an oxide film on the surface of the semiconductor substrate to form a mask;

forming a trench in one of the well regions for forming the trench lateral MOSFET using the oxide mask;

forming an expanded drain region of the second conductivity type around the trench;

forming a thick oxide film on an inner side wall of the trench;

etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask;

removing the oxide film on the surface of the semiconductor substrate;

forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed;

forming a selective oxide film using the nitride mask;

forming gate oxide films inside the trench and on the surface of one of the well regions for forming the planar MOSFET;

forming gate electrodes on the respective gate oxide films;

forming a base region of a first conductivity type in the bottom of the trench;

forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, and forming a drain region of the second conductivity type outside an upper portion of the trench;

selectively forming diffusion regions of the first conductivity type in the well region of the second conductivity type for forming the planar MOSFET, one of the diffusion regions operating as a source or a drain of the planar MOSFET and the other one of the diffusion regions operating as a drain or a source of the planar MOSFET;

forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench;

removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region;

filling the trench with a contact electrode; and

forming a metal electrode connected to the contact electrode, forming metal electrodes connected to the gate electrodes, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.

3. A method of manufacturing a semiconductor integrated circuit device having a semiconductor substrate, a planar bipolar transistor exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising:

forming two or more well regions of a second conductivity type in a surface of the semiconductor substrate;

forming an oxide film on the surface of the semiconductor substrate to form a mask;

forming a trench in one of the well regions for forming the trench lateral MOSFET using the oxide mask;

forming an expanded drain region of the second conductivity type around the trench;

forming a thick oxide film on an inner side wall of the trench;

etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask;

removing the oxide film on the surface of the semiconductor substrate;

forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed;

forming a selective oxide film using the nitride mask;

forming a gate oxide film inside the trench;

forming a gate electrode on the gate oxide film;

forming a base region of a first conductivity type selectively in the bottom of the trench and forming a base region of the first conductivity type selectively in one of the well regions of the second conductivity type for forming the planar bipolar transistor;

forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, and forming a drain region of the second conductivity type outside an upper portion of the trench;

selectively forming a first diffusion region of the second conductivity type in the well region of the second conductivity type for forming the planar bipolar transistor, the first diffusion region operating as an emitter or a collector of the planar bipolar transistor;

selectively forming a second diffusion region of the second conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the second diffusion region operating as a collector or an emitter of the planar bipolar transistor;

selectively forming a third diffusion region of the first conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the third diffusion region operating as a base of the planar bipolar transistor;

forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench;

removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region;

filling the trench with a contact electrode; and

forming a metal electrode connected to the contact electrode, forming a metal electrode connected to the gate electrode, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.

9. The method of claims 3 or 4, wherein an impurity concentration in the base region of the first conductivity type formed in the bottom of the trench and an impurity concentration in the base region of the first conductivity type formed selectively in the well region of the second conductivity type for forming the planar bipolar transistor differ from one another.

4. A method of manufacturing a semiconductor integrated circuit device including a semiconductor substrate, a first planar MOSFET exhibiting a low breakdown voltage on the semiconductor substrate, a second planar MOSFET exhibiting a low breakdown voltage on the semiconductor substrate, a planar bipolar transistor exhibiting a low breakdown voltage on the semiconductor substrate, and a trench lateral MOSFET exhibiting a high breakdown voltage, the method comprising:

forming one or more well regions of a first conductivity type and three or more well regions of a second conductivity type in a surface of the semiconductor substrate;

forming an oxide film on the surface of the semiconductor substrate to form a mask;

forming a trench in one of the well regions of the second conductivity type for forming the trench lateral MOSFET using the oxide mask;

forming an expanded drain region of the second conductivity type around the trench;

forming a thick oxide film on an inner side wall of the trench;

etching a bottom of the trench to a level that is deeper than a lower edge of the expanded drain region using the thick oxide film as a mask;

removing the oxide film on the surface of the semiconductor substrate;

forming a nitride mask on the surface of the semiconductor substrate and an inner surface of the trench, the mask being a nitride film, and a part thereof being selectively removed;

forming a selective oxide film using the nitride mask;

forming gate oxide films inside the trench on one of the well regions of the first conductivity type for forming the first planar MOSFET, and on one of the well regions of the second conductivity type for forming the second planar MOSFET;

forming gate electrodes on the respective gate oxide films;

forming a base region of the first conductivity type in the bottom of the trench and a base region of the first conductivity type selectively in one of the well regions of the second conductivity type for forming the planar bipolar transistor;

forming a source region of the second conductivity type in the bottom of the trench, the base region being deeper than the source region, and forming a drain region of the second conductivity type outside an upper portion of the trench;

selectively forming a first diffusion region of the second conductivity type in the well region of the first conductivity type for forming the first planar MOSFET, the first diffusion region operating as a source or a drain of the first planar MOSFET;

selectively forming a second diffusion region of the second conductivity type in the well region of the first conductivity type for forming the first planar MOSFET, the second diffusion region operating as a drain or a source of the first planar MOSFET;

selectively forming a third diffusion region of the second conductivity type in the well region of the second conductivity type for forming the planar bipolar transistor, the third diffusion region operating as an emitter or a collector of the planar bipolar transistor;

selectively forming a fourth diffusion region of the second conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the fourth diffusion region operating as a collector or an emitter of the planar bipolar transistor;

selectively forming a fifth diffusion region of the first conductivity type in the well region of the second conductivity type for forming the second planar MOSFET, the fifth diffusion region operating as a source or a drain of the second planar MOSFET;

forming a sixth diffusion region of the first conductivity type in the well region of the second conductivity type for forming the second planar MOSFET, the fifth diffusion region operating as a drain or a source of the second planar MOSFET;

forming a seventh diffusion region of the first conductivity type in the base region of the first conductivity type, which is formed in the well region of the second conductivity type for forming the planar bipolar transistor, the seventh diffusion region operating as a base of the planar bipolar transistor;

forming an interlayer insulation film on the surface of the semiconductor substrate and inside the trench;

removing a portion of the interlayer insulation film on the bottom of the trench to expose the source region;

filling the trench with a contact electrode; and

forming a metal electrode connected to the contact electrode, forming metal electrodes connected to the gate electrodes, forming a metal electrode connected to the drain region, and forming metal electrodes connected to the respective diffusion regions.