Method for manufacturing semiconductor device

• US 20050142764A1
• Filed: 06/28/2004
• Published: 06/30/2005
• Est. Priority Date: 12/29/2003
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.), STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Seung Cheol, Park, Sang Wook
• Application Number:
  US10/878,173
• Publication Number:
  US 20050142764A1
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The present invention discloses a method for manufacturing a semiconductor device which forms a thick gate oxide film in a high voltage region and a thin tunnel oxide film in a cell region. The method for manufacturing the semiconductor device reduces a process time and improves uniformity of the gate oxide film in the high voltage region, by growing the gate oxide film in the high voltage region at a thickness of about 400 Å, and removing a residual nitride film in the cell region by performing an etching process using a BOE solution and an etching process using H₃PO₄ for 120 seconds and 12 minutes, respectively.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

sequentially forming a pad oxide film, a nitride film and an oxide film on a semiconductor substrate, and exposing the pad oxide film by removing the oxide film and the nitride film in a high voltage region;

removing the pad oxide film in the high voltage region according to a pre-cleaning process, and removing the oxide film in a cell region;

forming a gate oxide film in the high voltage region according to a first oxidation process;

removing the residual nitride film in the cell region, by performing an etching process using a predetermined etching solution and an etching process using H₃PO₄ for 120 seconds and 12 minutes, respectively, the gate oxide film in the high voltage region being partially recessed;

removing the pad oxide film in the cell region according to a pre-cleaning process, the gate oxide film in the high voltage region being partially recessed; and

forming a tunnel oxide film in the cell region according to a second oxidation process.

2. The method of claim 1, wherein the gate oxide film is formed at a thickness of about 400 Å

.

3. The method of claim 1, wherein the first oxidation process is performed at a temperature of 700 to 850°

C. according to a wet or dry method.

4. The method of claim 1, wherein the etching solution is a BOE solution or an HF solution.

5. The method of claim 1, wherein the etching process using H₃PO₄ is performed at a temperature of 100 to 160°

C.

6. The method of claim 1, wherein the gate oxide film in the high voltage region is partially grown by the second oxidation process.