Partitioning memory

• US 20050144411A1
• Filed: 12/30/2003
• Published: 06/30/2005
• Est. Priority Date: 12/30/2003
• Status: Abandoned Application

• Current Assignee: Buntrock Industries Incorporated, Intel Corporation
• Original Assignee: Buntrock Industries Incorporated
• Inventors: Meng, David Qiang
• Application Number:
  US10/750,423
• Publication Number:
  US 20050144411A1
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

A method includes partitioning a memory device to produce a first group of memory entries being accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

Claims

1. A method comprising:

partitioning a memory device to produce a first group of memory entries being accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

2. The method of claim 1, further comprising:

partitioning a memory entry in the first group of memory entries into sub-entries.

3. The method of claim 1, further comprising:

selecting the first group of memory entries for accessing in parallel.

4. The method of claim 1 wherein the memory device is included in a multithreaded engine of a packet processor.

5. The method of claim 1 wherein the first group of memory entries store a first type of data and the second group of memory entries store a second type of data.

6. The method of claim 2 wherein the memory entry includes at least two subentries.

7. The method of claim 2 wherein the memory entry includes a combination of subentries.

8. A computer program product, tangibly embodied in an information carrier, the computer program product being operable to cause a machine to:

partition a memory device to produce a first group of memory entries being accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

9. The computer program product of claim 8 being further operable to cause a machine to:

partition a memory entry in the first group of memory entries into sub-entries.

10. The computer program product of claim 8 being further operable to cause a machine to:

select the first group of memory entries for accessing in parallel.

11. A computer program product of claim 8 wherein the memory device is included in a multithreaded engine of a packet processor.

12. The computer program product of claim 8 wherein the first group of memory entries store a first type of data and the second group of memory entries store a second type of data.

13. The computer program product of claim 9 wherein the memory entry includes at least two subentries.

14. The computer program product of claim 9 wherein the memory entry includes a combination of subentries.

15. A content-addressable memory (CAM) manager comprises:

a process to partition a memory device to produce a first group of memory entries being accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

16. The CAM manager of claim 15 further comprising:

a process to partition a memory entry in the first group of memory entries into sub-entries.

17. The CAM manager of claim 15 further comprising:

a process to select the first group of memory entries for accessing in parallel.

18. A system comprising:

a memory device capable of being partitioned to produce a first group of memory entries that is accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

19. The system of claim 18 wherein a memory entry in the first group of memory entries is capable of being partitioned into sub-entries.

20. The system of claim 18 wherein the first group of memory entries is further capable of being selected for accessing in parallel.

21. A packet forwarding device comprising:

an input port for receiving a packet;

and output port for delivering the received packet; and

a memory device capable of being partitioned to produce a first group of memory entries that is accessible in parallel and selectable independent of a second group of memory entries in the memory device that is accessible in parallel.

22. The packet forwarding device of claim 21 wherein a memory entry in the first group of memory entries is capable of being partitioned into sub-entries.

23. The packet forwarding device of claim 21 wherein the first group of memory entries is further capable of being selected for accessing in parallel.

24. A content-addressable memory (CAM) comprising:

a first group of memory entries being accessible in parallel and selectable independent of a second group of memory entries in the CAM that is accessible in parallel.

25. The CAM of claim 24 wherein a memory entry in the first group of memory entries is capable of being partitioned into sub-entries.

26. The CAM of claim 24 wherein the first group of memory entries is further capable of being selected for accessing in parallel.