Method and system for allowing code to be securely intialized in a computer

• US 20050144476A1
• Filed: 02/25/2005
• Published: 06/30/2005
• Est. Priority Date: 11/22/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: England, Paul, Willman, Bryan
• Granted Patent: US 7,543,335 B2
• Time in Patent Office: Days
• US Class Current: 726/17
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A memory controller prevents CPUs and other I/O bus masters from accessing memory during a code (for example, trusted core) initialization process. The memory controller resets CPUs in the computer and allows a CPU to begin accessing memory at a particular location (identified to the CPU by the memory controller). Once an initialization process has been executed by that CPU, the code is operational and any other CPUs are allowed to access memory (after being reset), as are any other bus masters (subject to any controls imposed by the initiated code).

Claims

1. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:

booting, based on untrustworthy code, a computer;

loading a trusted core into memory; and

initiating secure execution of the trusted core by;

mapping a central processing unit reset vector to an initialization vector;

resetting each of one or more central processing units in the computer;

receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units;

returning, in response to the read request, the initialization vector to the one central processing unit; and

allowing the one central processing unit to access the memory beginning with the initialization vector.

2. One or more computer-readable media as recited in claim 1, wherein the initialization vector is an address within the trusted core in the memory.

3. One or more computer-readable media as recited in claim 1, wherein the plurality of instructions further causes the one or more processors to perform acts including:

re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

returning, in response to any other read request corresponding to the central processing unit reset vector from another of the one or more central processing units, the additional central processing unit start vector.

4. One or more computer-readable media as recited in claim 3, wherein the initialization vector is an address within the trusted core in the memory and wherein the additional central processing unit start vector and the initialization vector are different addresses within the trusted core in the memory.

5. A system comprising:

means for booting, based on untrustworthy code, a computer;

means for loading a trusted core into memory; and

means for initiating secure execution of the trusted core including;

means for mapping a central processing unit reset vector to an initialization vector;

means for resetting each of one or more central processing units in the computer;

means for receiving, after the mapping and the resetting, a read request corresponding to the central processing unit reset vector from one of the one or more central processing units;

means for returning, in response to the read request, the initialization vector to the one central processing unit; and

means for allowing the one central processing unit to access the memory beginning with the initialization vector.

6. A system as recited in claim 5, wherein the initialization vector is an address within the trusted core in the memory.

7. A system as recited in claim 5, further comprising:

means for re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

means for returning, in response to any other read request corresponding to the central processing unit reset vector from another of the one or more central processing units, the additional central processing unit start vector.

8. A system as recited in claim 7, wherein the initialization vector is an address within the trusted core in the memory and wherein the additional central processing unit start vector and the initialization vector are different addresses within the trusted core in the memory.

9. One or more computer-readable media having stored thereon a plurality of instructions that, when executed by one or more processors of a computer, causes the one or more processors to perform acts including:

allowing a computer to begin operation based on untrustworthy code;

loading, under the control of the untrustworthy code, additional code into memory;

initiating execution of the additional code in a secure manner despite the untrustworthy code in the computer;

mapping a central processing unit reset vector to an initialization vector;

receiving a read request corresponding to the central processing unit reset vector from one central processing unit;

returning, in response to the read request, the initialization vector to the one central processing unit; and

allowing the one central processing unit to access the memory beginning with the initialization vector.

10. One or more computer-readable media as recited in claim 9, wherein the initiating further comprises initiating execution of the additional code in a secure manner despite both the untrustworthy code in the computer and other pre-existent state of the computer.

11. One or more computer-readable media as recited in claim 9, wherein the initiating execution of the additional code in a secure manner comprises:

preventing each of one or more central processing units in the computer from accessing the memory;

preventing each of one or more bus masters in the computer from accessing the memory;

resetting each of the one or more central processing units;

allowing the one central processing unit to access the memory and execute a code initialization process; and

after execution of the code initialization process, allowing any other central processing units and any of the one or more bus masters to access the memory.

12. One or more computer-readable media as recited in claim 9, wherein the initiating comprises initiating execution of the additional code in a secure manner without requiring any additional bus transactions to be supported by a processor in the computer.

13. One or more computer-readable media as recited in claim 9, wherein the plurality of instructions further cause the one or more processors to perform acts including:

re-mapping the central processing unit reset vector to an additional central processing unit start vector after returning the initialization vector to the one central processing unit; and

returning, in response to any other read request corresponding to the central processing unit reset vector from another central processing unit, the additional central processing unit start vector.

14. One or more computer-readable media as recited in claim 9, wherein the loading the additional code comprises copying different portions of the additional code from a plurality of different sources including one or more of:

a local mass storage device, a remote device, and a local chipset.