Variable power consumption levels in a hard disk drive

• US 20050144491A1
• Filed: 12/22/2004
• Published: 06/30/2005
• Est. Priority Date: 12/24/2003
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Zayas, Fernando A.
• Application Number:
  US11/020,383
• Publication Number:
  US 20050144491A1
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G11B 19/00 Driving, starting, stopping record carriers not specifically of filamentary or web form, or of supports therefor; Control thereof; Control of operating function ; Driving both disc and head
• CPC Class Codes: G11B 19/26 Speed-changing arrangements; Reversing arrangements; Drive-transfer means therefor
• CPC Class Codes: G11B 5/5565 system adaptation for compensation of variations of physical parameters, e.g. temperature
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Attributes of a hard disk drive are stepped between different power consumption levels to optimize the trade-off between minimizing power consumption and maximizing performance depending on whether AC or battery power is used. One attribute is the clock speed which can be changed for a number of disk drive components including the processor, the external interface bus and the memory interface bus. The system power supply voltage can further be changed in a number of components integrated together on an application specific integrated circuit (ASIC). Further, spindle motor rotation speed can be changed, or the spindle motor spun-down. Further, actuator movement by the VCM can be controlled to provide faster movement during track seek operations when high performance is desired. Additionally, write-back caching parameters are adjusted based on the source of power for the hard drive, be it battery, AC power, or a combination.

Claims

1. An apparatus comprising:

a first terminal configured to connect to an AC power supply;

a second terminal configured to connect to a battery; and

a hard disk drive system coupled to receive power from at least one of the first terminal and second terminal, the hard disk drive configured to increase power consumption in a high performance mode when the AC power supply is connected to the first terminal relative to a low performance mode when the AC power is disconnected from the first terminal and the battery is connected to the second terminal.

2. The apparatus of claim 1 further comprising:

a power supply coupling the first and second terminals to the hard disk drive system, the power supply configured to provide power from at least one of the first and second connecting terminals to the hard disk drive system, the power supply further providing a performance indication output to the hard disk drive system indicating the high performance mode when the AC power supply is connected to the first terminal, and the low performance mode when the AC power supply is disconnected from the first terminal and the battery is connected to the second terminal.

3. The apparatus of claim 2, wherein the power supply includes a power converter comprising a standby uninterrupted power supply (UPS) having a switch configured to connect power to the output of the power control circuit from the second terminal when the battery is connected and the AC power supply is disconnected, and to connect power from the first terminal to the output terminal when the AC power supply is connected.

4. The apparatus of claim 3, wherein the power supply comprises:

an AC-DC converter connecting the first terminal to a first switching node of the standby UPS switch, the AC-DC converter configured to converting AC power received from the AC power supply to a DC voltage provided to the standby UPS switch;

a line connecting the second terminal to a second switching node of the standby UPS switch; and

a DC-DC converter having an input connected to a common terminal of the standby UPS switch, and having outputs providing a plurality of voltage outputs. to the hard disk drive; and

a power mode detection circuit coupled to the first terminal and the second terminal, the power mode circuit detecting connection of the AC power supply and the battery, and controlling the standby UPS switch to supply power from the first terminal when the AC power supply is connected, and to supply power from the second terminal when the AC power supply is disconnected and the battery is connected, the power mode circuit further providing the performance mode indication to the hard disk drive based on the detected connection.

5. The apparatus of claim 2, wherein the power supply includes a continuous uninterrupted power supply (UPS) providing a continuous current from the battery to the power control circuit output terminal when a source of power is changed between the AC power supply and the battery.

6. The apparatus of claim 5, wherein the power supply comprises:

a battery charger having an input connected to the first terminal and an output configured for connection to the battery; and

a DC-DC converter having an input connected to the second terminal and outputs providing a plurality of voltages to the hard disk drive;

a power mode detection circuit coupled to the first terminal and the second terminal, the power mode circuit detecting connection of the AC power supply and the battery and providing the performance mode indication to the hard disk drive based on the detected connection.

7. The apparatus of claim 2, wherein the disk drive system comprises:

a cache memory;

a memory controller coupled to the cache memory, the memory controller causing changes to data written to a rotatable disk to be stored in the cache memory; and

a power management circuit which receives a performance indication from the power supply, wherein the power management circuit provides a signal to the memory controller to cause changes to data written in the cache memory to be written to the rotatable disk within a predetermined time limit when the high performance mode is indicated, and not written to the rotatable disk when the low performance mode is indicated.

8. The apparatus of claim 2, wherein the disk drive system comprises:

a cache memory;

a memory controller coupled to the cache memory, the memory controller causing changes to data written to a rotatable disk to be stored in the cache memory; and

a power management circuit which receives the performance indication from the power supply, wherein the power management circuit provides a signal to the memory controller to cause changes to data written in the cache memory to be written to the rotatable disk within a first time limit when the high performance mode is indicated, and written to the rotatable disk within a second time less than the first time when the low performance mode is indicated.

9. A disk drive system comprising:

an electric motor connected to enable data to be read from a rotatable disk; and

a motor driver connected to apply current to the electric motor to obtain a desired operation speed of the motor, and to receive a power conservation mode signal, wherein a first speed is selected when the power conservation mode signal indicates a high performance mode, and wherein a second speed less than the first rotation speed is selected when the power conservation mode signal indicates a low performance mode.

10. The disk drive system of claim 9, wherein the electric motor is a spindle motor.

11. The disk drive system of claim 9, wherein the electric motor is a voice control motor (VCM).

12. The disk drive system of claim 9, further comprising:

a power management circuit receiving a signal indicating when power is provided by an AC power source, the power management circuit providing a signal to control the motor driver to provide operation in the high performance mode when power is provided by the AC power source, and to operate in the low performance mode when the AC power source is disconnected and power is provided by the battery.

13. A hard disk drive system comprising:

a clock signal generation circuit connected to selectively provide clock signals to one or more components of the hard disk drive, wherein a first one of the clock signals is provided having a first clock rate when the disk drive system is in a high performance mode, and wherein a second one of the clock signals is provided having a second clock rate less which is less than the first clock rate when the disk drive system is in a low performance mode to reduce power consumption by the hard disk drive.

14. The apparatus of claim 13, wherein the one or more components of the hard disk drive system comprise:

an interface bus configured for transmitting data read from the magnetic media to components external to the hard disk drive, and for transmitting data from components external to the disk drive to be written to the magnetic media, wherein data transmitted on the interface bus is clocked by the first and second clock signals from the clock signal generation circuit.

15. The apparatus of claim 13, wherein the components of the hard disk drive system comprise:

a processor coupled to receive data read from the magnetic media by the transducer and to provide data to be written by the transfer to the magnetic media; and

an interface bus configured for transmitting data read from the magnetic media between the processor and components external to the hard disk drive, and for transmitting data from components external to the disk drive to be written to the magnetic media by the processor,

wherein the interface bus and the processor carry signals clocked by the first and second clock signals from the clock signal generation circuit.

16. The apparatus of claim 13, wherein the components of the hard disk drive system comprise:

a processor coupled to receive data read from the magnetic media by the transducer and to provide data to be written by the transducer to the magnetic media; and

an SDRAM coupled to the processor by a memory bus for storing code executable by the processor to enable the processor to receive the data read from the magnetic media and to provide data to be written to the magnetic media, wherein the memory bus carries signals clocked by the first and second clock signals from the clock signal generation circuit.

17. The apparatus of claim 13, wherein the components of the hard disk drive system comprise:

a processor coupled to receive data read from the magnetic media by the transducer and to provide data to be written by the transfer to the magnetic media;

an interface bus configured for transmitting data read from the magnetic media between the processor and components external to the hard disk drive, and for transmitting data from components external to the disk drive to be written to the magnetic media by the processor; and

an SDRAM coupled to the processor by a memory bus for storing code executable by the processor to enable the processor to receive the data read from the magnetic media and to provide data to be written to the magnetic media, wherein the memory bus carries signals clocked by the first and second clock signals from the clock signal generation circuit,

wherein the interface bus, the SDRAM, and the processor carry signals clocked by the first and second clock signals from the clock signal generation circuit.

18. The apparatus of claim 13, wherein the one or more components of the hard disk drive system comprise:

a read/write channel receiving signals read by the transducer from the rotatable disk, wherein the clock signal generation circuit is connected to selectively provide the clock signals to the read/write channel.

19. The apparatus of claim 13, wherein the clock signal generation circuit comprises:

a first phase locked loop configured for receiving a reference clock signal and generating the first clock signal having the first clock rate;

a second phase locked loop configured for receiving the reference clock signal and generating the second clock signal having the second clock rate; and

a clock switch connected to the first and second phase locked loops, the clock switch configured for selectively providing one of the first and second clock signals as controlled by the clock signal generation circuit.

20. The apparatus of claim 13, wherein the clock signal generation circuit comprises:

a phase locked loop having a clock signal input for connecting to an oscillator operating at a fixed frequency, the phase locked loop having a frequency control input and an output, the frequency control input for receiving a signal from the clock signal generation circuit to enable the phase locked loop to provide one of the first and second clock signals.