Digital reliability monitor having autonomic repair and notification capability

• US 20050144524A1
• Filed: 06/08/2004
• Published: 06/30/2005
• Est. Priority Date: 12/04/2003
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bonaccio, Anthony R., Ventrone, Sebastian T., Tonti, William R., LeStrange, Michael
• Application Number:
  US10/863,194
• Publication Number:
  US 20050144524A1
• Time in Patent Office: Days
• US Class Current: 714/27
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

A method a circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, the repair processor adapted to (a) replace the original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of predetermined cycle counts.

Claims

1. An integrated circuit, comprising:

an original circuit;

one or more redundant circuits; and

a repair processor, including a clock cycle counter adapted to count pulses of a pulsed signal, said repair processor adapted to (a) replace said original circuit with a first redundant circuit or (b) adapted to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with said selected redundant circuit each time said cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

2. The integrated circuit of claim 1, further including:

a robust redundant circuit; and

said repair processor further adapted to replace said last redundant circuit with said robust redundant circuit when said clock cycle counter reaches a last count of said set of predetermined cycle counts.

3. The integrated circuit of claim 1, wherein said repair processor is further adapted to continuously replace a last selected circuit with a different circuit, said last selected circuit and said different circuit independently selected from the group consisting of said original circuit and said one or more redundant circuits, in the sequence from said original circuit to said first redundant circuit through said last redundant circuit and back to said original circuit, each time said clock cycle counter reaches a predetermined count of a set of additional pre-determined cycle counts.

4. The integrated circuit of claim 3, further including:

an error detection circuit adapted to determine if said original circuit or any of said one or more redundant circuits has failed;

a tracking register coupled between said error detection and said repair processor, said tracking register adapted to store information marking a failed original circuit or a failed redundant circuit as a failed circuit; and

said repair processor is further adapted to not replace said original circuit or any redundant circuit with a failed circuit.

5. The integrated circuit of claim 1, further including:

a stress reduction circuit coupled to said original circuit and said one or more redundant circuits and responsive to said repair processor; and

said stress reduction circuit adapted to modify one or more operating parameters of said original circuit, of said one or more redundant circuits or of said original circuit and said one or more redundant circuits when said clock cycle counter reaches a particular pre-determined cycle count.

6. The integrated circuit of claim 1, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits adapted to select a frequency of said pulsed signal, pulse generating circuits adapted to select said frequency of said pulsed signal, bias circuits adapted to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.

7. The integrated circuit of claim 1, wherein said pulsed signal is a clock signal.

8. The integrated circuit of claim 1, wherein said original circuit and said one or more redundant circuits are selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual devices, a transistor, a diode, a resistors, capacitor, an inductor and a wire.

9. The integrated circuit of claim 1, further including:

wherein said clock cycle counter comprises one or more sub-clock cycle counters each having a latch adapted to store a running total count of pulses of said pulsed signal; and

a decode circuit coupled to said latches of said sub-clock cycle counters, said decode circuit adapted to replace a particular sub-clock cycle counter with a different sub-clock cycle counter each time said running total count of pulses of said pulsed signal reaches predetermined counts.

10. A method of preventing failure in an integrated circuit, comprising:

providing an original circuit;

providing one or more redundant circuits; and

providing a repair processor, including a clock cycle counter for counting pulses of a pulsed signal, said repair processor for (a) replacing said original circuit with a first redundant circuit or for (b) in sequence from a second redundant circuit to a last redundant circuit, selecting another redundant circuit and replacing a previously selected redundant circuit with said selected redundant circuit each time said clock cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

11. The method of claim 10, further including:

providing a robust redundant circuit; and

adapting said repair processor for replacing said last redundant circuit with said robust redundant circuit when said clock cycle counter reaches a last count of said set of predetermined cycle counts.

12. The method of claim 10, further including:

adapting said repair processor for continuously replacing a last selected circuit with a different circuit, said last selected circuit and said different circuit independently selected from the group consisting of said original circuit and said one or more redundant circuits, in the sequence from original circuit to said first redundant circuit through said last redundant circuit and back to said original circuit, each time said clock cycle counter reaches a predetermined count of a set of additional pre-determined cycle counts.

13. The method of claim 12, further including:

providing an error detection circuit for determining if said original circuit or any of said one or more redundant circuits has failed;

providing a tracking register coupled between said error detection and said repair processor, said tracking register for storing information marking a failed original circuit or a failed redundant circuit as a failed circuit; and

adapting said repair processor to not replace said original circuit or any redundant circuit with a failed circuit.

14. The method of claim 10, further including:

providing a stress reduction circuit coupled to said original circuit and said one or more redundant circuits and responsive to said repair processor, said repair processor for modifying one or more operating parameters of said original circuit, of said one or more redundant circuits or of said original circuit and said one or more redundant circuits when said clock cycle counter reaches a particular predetermined cycle count.

15. The method of claim 10, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits adapted to select a frequency of said pulsed signal, pulse generating circuits adapted to select said frequency of said pulsed signal, bias circuits adapted to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.

16. The method of claim 10, wherein said pulsed signal is a clock signal.

17. The method of claim 10, wherein said original circuit and said one or more redundant circuits are selected from the group consisting of a digital circuit, an analog circuit, a memory circuit, a latch, a logic gate, a group of logic gates, an individual devices, a transistor, a diode, a resistors, capacitor, an inductor and a wire.

18. The method of claim 10, further including:

providing said clock cycle counter with one or more sub-clock cycle counters each having a latch for storing a running total count of pulses of said pulsed signal; and

providing a decode circuit coupled to said latches of said sub-clock cycle counters, said decode circuit for replacing a particular sub-clock cycle counter with a different sub-clock cycle counter each time said running total count of pulses of said pulsed signal reaches predetermined counts.

19. An integrated circuit, comprising:

an original circuit; and

a stress reduction circuit coupled to said original circuit and coupled to and responsive to a repair processor, said repair processor including a clock cycle counter adapted to count pulses of a pulsed signal and said stress reduction circuit adapted to modify one or more operating parameters of said original circuit when said clock cycle counter reaches a particular predetermined cycle count.

20. The integrated circuit of claim 19, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits adapted to select a frequency of said pulsed signal, pulse generating circuits adapted to select said frequency of said pulsed signal, bias circuits adapted to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.

21. A method for preventing failure of an integrated circuit, comprising:

providing an original circuit;

providing a repair processor, said repair processor including a clock cycle counter for counting pulses of a pulsed signal and

providing a stress reduction circuit coupled to said original circuit and coupled to and responsive to said repair processor, said stress reduction circuit for modifying one or more operating parameters of said original circuit when said clock cycle counter reaches a particular pre-determined cycle count.

22. The method of claim 22, wherein said stress reduction circuit is selected from the group consisting of voltage regulator circuits, switching circuits adapted to select a frequency of said pulsed signal, pulse generating circuits adapted to select said frequency of said pulsed signal, bias circuits adapted to select a bias voltage to apply to bodies of transistors in said original circuit, said one or more redundant circuits or both said original circuit and said one or more redundant circuits, and combinations thereof.