Longest prefix match (LPM) algorithm implementation for a network processor
First Claim
1. An apparatus fabricated on a semiconductor substrate for determining a longest prefix match for a variable length search key, comprising:
- an embedded processor complex including a plurality of protocol processors and an internal control point processor that provide frame processing;
a plurality of hardware accelerator co-processors accessible to each protocol processor and providing high speed pattern searching, data manipulation, and frame parsing;
a plurality of programmable memory devices that store a plurality of data structures that represent at least one search tree, wherein the data structures include a direct table, a pattern search control block, a bird and a leaf; and
an control memory arbiter that controls the access of each protocol processor to the plurality of memory devices.
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Abstract
Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
73 Citations
18 Claims
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1. An apparatus fabricated on a semiconductor substrate for determining a longest prefix match for a variable length search key, comprising:
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an embedded processor complex including a plurality of protocol processors and an internal control point processor that provide frame processing;
a plurality of hardware accelerator co-processors accessible to each protocol processor and providing high speed pattern searching, data manipulation, and frame parsing;
a plurality of programmable memory devices that store a plurality of data structures that represent at least one search tree, wherein the data structures include a direct table, a pattern search control block, a bird and a leaf; and
an control memory arbiter that controls the access of each protocol processor to the plurality of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data structure for use in database comprising:
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(a) a table having a plurality of entries wherein at least one entry includes a first field in which a first leaf bit pattern is stored, a second field in which a bit value indicating the Next Bit to Test (NBT) is stored and a third field in which a Next Pointer Address (NPA) is stored; and
(b) at least one Pattern Search Control Block (PSCB) operatively coupled to the at least one entry, said PSCB including two entries with each entry being structured with fields identical to those listed in (a). - View Dependent Claims (12, 13, 14, 15)
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16. A method to correlate a search string against a database comprising the acts of:
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(a) providing the database having data structure including a table with N entries N>
1, at least one entry including a first field in which a first leaf bit pattern is stored, a second field in which a bit value is stored and a third field in which a Next Pointer Address (NPA) is stored; and
b. at least one Pattern Search Control Block (PSCB) operatively coupled to the at least one entry, said PSCB including two entries with each entry being structured with fields substantially similar to those listed in (a);
using M bits of the search string as an address to index into the at least one entry; and
reading the entry to determine what action next to pursue in correlating the search string with the database. - View Dependent Claims (17, 18)
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Specification