[MULTI-LEVEL MEMORY CELL]

• US 20050145919A1
• Filed: 01/02/2004
• Published: 07/07/2005
• Est. Priority Date: 01/02/2004
• Status: Active Grant

• Current Assignee: Powerchip Semiconductor Manufacturing Corp. (Powerchip Technology Corporation)
• Original Assignee: Powerchip Semiconductor Corporation (Powerchip Technology Corporation)
• Inventors: Huang, Chiu-Tsung, Chang, Ko-Hsing
• Granted Patent: US 7,164,177 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.

Claims

1. A multi-level memory cell, comprising:

a substrate;

a gate disposed over the substrate;

a source region and a drain region configured in the

substrate on each side of the gate; and

a bottom silicon oxide/silicon nitride/top silicon oxide layer disposed between the gate and the substrate, wherein the top silicon oxide has a first portion and a second portion from the direction of the source region to drain region, and the first portion has a thickness different from the second portion.

2. The multi-level memory cell of claim 1, wherein the cell further comprises a pair of spacers disposed on each sidewall of the gate.

3. The multi-level memory cell of claim 1, wherein the cell further comprises lightly doped regions disposed in the substrate underneath the spacers.

4. The multi-level memory cell of claim 1, wherein material constituting the spacers comprises silicon oxide.

5. The multi-level memory cell of claim 1, wherein the bottom silicon oxide layer has a thickness between about 20 Å

to 40 Å

.

6. The multi-level memory cell of claim 1, wherein the silicon nitride layer has a thickness between about 40 Å

to 60 Å

.

7. A multi-level memory cell, comprising:

a substrate;

a gate disposed on the substrate;

a source region and a drain region configured in the substrate on each side of the gate;

a tunneling dielectric layer disposed between the gate and the substrate;

a charge-trapping layer disposed between the tunneling dielectric layer and the gate; and

a top dielectric layer disposed between the charge-trapping layer and the gate, wherein the top dielectric layer has at least two portions from the direction of the source region to drain region, and each portion has different thickness.

8. The multi-level memory cell of claim 7, wherein material constituting the charge-trapping layer comprises silicon nitride.

9. The multi-level memory cell of claim 7, wherein the cell further comprises a pair of spacers disposed on each sidewall of the gate.

10. The multi-level memory cell of claim 7, wherein the cell further comprises lightly doped regions configured in the substrate underneath the spacers.

11. The multi-level memory cell of claim 7, wherein material constituting the spacers comprises silicon oxide.

12. The multi-level memory cell of claim 7, wherein the tunneling dielectric layer has a thickness between about 20 Å

to 40 Å

.

13. The multi-level memory cell of claim 7, wherein the charge-trapping layer has a thickness between about 40 Å

to 60 Å

.

14. The multi-level memory cell of claim 7, wherein material constituting the tunneling dielectric layer comprises silicon oxide.

15. The multi-level memory cell of claim 7, wherein material constituting the top dielectric layer comprises silicon oxide.