[MULTI-LEVEL MEMORY CELL]
First Claim
1. A multi-level memory cell, comprising:
- a substrate;
a gate disposed over the substrate;
a source region and a drain region configured in the substrate on each side of the gate; and
a bottom silicon oxide/silicon nitride/top silicon oxide layer disposed between the gate and the substrate, wherein the top silicon oxide has a first portion and a second portion from the direction of the source region to drain region, and the first portion has a thickness different from the second portion.
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Accused Products
Abstract
A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.
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Citations
15 Claims
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1. A multi-level memory cell, comprising:
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a substrate;
a gate disposed over the substrate;
a source region and a drain region configured in the substrate on each side of the gate; and
a bottom silicon oxide/silicon nitride/top silicon oxide layer disposed between the gate and the substrate, wherein the top silicon oxide has a first portion and a second portion from the direction of the source region to drain region, and the first portion has a thickness different from the second portion. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A multi-level memory cell, comprising:
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a substrate;
a gate disposed on the substrate;
a source region and a drain region configured in the substrate on each side of the gate;
a tunneling dielectric layer disposed between the gate and the substrate;
a charge-trapping layer disposed between the tunneling dielectric layer and the gate; and
a top dielectric layer disposed between the charge-trapping layer and the gate, wherein the top dielectric layer has at least two portions from the direction of the source region to drain region, and each portion has different thickness. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification