Nonvolatile semiconductor memory cell and method of manufacturing the same
First Claim
1. A nonvolatile semiconductor memory cell comprising:
- a semiconductor substrate;
a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on the semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and
gate side-wall insulation films formed on both side surfaces of the stacked-gate structure, wherein the thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.
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Accused Products
Abstract
A stacked-gate structure includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate. The inter-electrode insulation film has a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer. Gate side-wall insulation films are formed on both side surfaces of the stacked-gate structure. The thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side. The width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.
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Citations
20 Claims
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1. A nonvolatile semiconductor memory cell comprising:
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a semiconductor substrate;
a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on the semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and
gate side-wall insulation films formed on both side surfaces of the stacked-gate structure, wherein the thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A nonvolatile semiconductor memory cell comprising:
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a semiconductor substrate;
a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on the semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and
gate side-wall insulation films formed on both side surfaces of the stacked-gate structure, wherein the width of the floating gate electrode in a channel length direction is 50 nm or less on a surface of the tunnel insulation film, and the thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in the channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.
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12. A method of manufacturing a nonvolatile semiconductor memory cell, comprising:
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forming a tunnel insulation film on a semiconductor substrate;
forming on the tunnel insulation film a first conductive layer that becomes a floating gate electrode;
forming on the first conductive layer an inter-electrode insulation film that includes a first oxidant barrier layer, which suppresses passage of oxidant, an intermediate insulation layer, and a second oxidant barrier layer, which suppresses passage of oxidant;
forming on the inter-electrode insulation film a second conductive layer that becomes a control gate electrode;
forming a stacked-gate structure by selectively etching the first conductive layer, the second conductive layer and the inter-electrode insulation film; and
forming gate side-wall insulation films on side parts of the floating gate electrode by oxidizing or oxynitriding side surfaces of the stacked-gate structure, each of the gate side-wall insulation films having a thickness increasing from the inter-electrode insulation film side toward the tunnel insulation film side. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A method of manufacturing a nonvolatile semiconductor memory cell, comprising:
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forming a tunnel insulation film on a semiconductor substrate;
forming on the tunnel insulation film a first conductive layer that becomes a floating gate electrode;
forming on the first conductive layer an inter-electrode insulation film that includes a first oxidant barrier layer, which suppresses passage of oxidant, an intermediate insulation layer, and a second oxidant barrier layer, which suppresses passage of oxidant;
forming on the inter-electrode insulation film a second conductive layer that becomes a control gate electrode lower-layer;
forming a third oxidant barrier layer on the second conductive layer;
forming a stacked-gate structure by selectively etching the first conductive layer, the second conductive layer, the inter-electrode insulation film and the third oxidant barrier layer;
forming first gate side-wall insulation films on side parts of the floating gate electrode and second gate side-wall insulation films on side parts of the control gate electrode lower-layer by oxidizing or oxynitriding side surfaces of the stacked-gate structure, each of the first gate side-wall insulation films having a thickness increasing from the inter-electrode insulation film side toward the tunnel insulation film side, and each of the second gate side-wall insulation films having a thickness decreasing from a central part thereof toward the oxidant barrier layers; and
removing the third oxidant barrier layer and then forming on the control gate electrode lower-layer a control gate electrode upper-layer that has a lower resistance than the control gate electrode lower-layer.
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20. A memory card comprising:
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a memory chip including a plurality of nonvolatile memory cells, and a controller that controls the memory chip, the memory chip and the controller being mounted on a single wiring board, wherein the memory cell comprises;
a stacked-gate structure that includes a tunnel insulation film, a floating gate electrode, an inter-electrode insulation film and a control gate electrode, which are stacked on a semiconductor substrate, the inter-electrode insulation film having a three-layer structure that includes a first oxidant barrier layer, an intermediate insulation layer and a second oxidant barrier layer; and
gate side-wall insulation films formed on both side surfaces of the stacked-gate structure, wherein the thickness of the gate side-wall insulation film increases, at a side portion of the floating gate electrode, from the inter-electrode insulation film side toward the tunnel insulation film side, and the width of the floating gate electrode in a channel length direction decreases from the inter-electrode insulation film side toward the tunnel insulation film side.
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Specification