Power transistor arrangement and method for fabricating it
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Accused Products
Abstract
When fabricating trench power transistor arrangements (1) with active cell array trenches (5) and passive connecting trenches (6), the cell array trenches (5) are provided in greater width than the connecting trenches (6). An auxiliary layer (24) is deposited conformally onto a lower field electrode structure (11) in the cell array trenches (5) and the connecting trenches (6) and is etched back as far as the top edge in the connecting trenches (6), which removes it from the cell array trenches (5). The auxiliary layer (24) allows the gate oxide (20) to be patterned without a complex mask process. An edge trench (7), with an electrode, on the potential of the field electrode structure (11) shields the cell array (3) from a drain potential.
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Citations
58 Claims
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1-29. -29. (canceled)
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30. A method for fabricating a power transistor arrangement, comprising:
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providing a cell array in a semiconductor substrate including a substrate surface;
providing a plurality of cell array trenches and at least one connecting trench connected to the plurality of cell array trenches within the cell array, wherein the width of each of the plurality of cell array trenches is greater than the width of the at least one connecting trench, and wherein the plurality of cell array trenches and at least one connecting trench extend below the substrate surface;
providing an insulating layer on the substrate surface and in the plurality of cell array trenches and at least one connecting trench;
applying a first conductive layer to the insulating layer;
at least partially removing the first conductive layer, wherein the first conductive layer forms a field electrode structure;
applying a conductive auxiliary layer to the insulating layer and the first conductive layer, wherein the at least one connecting trench is filled with the conductive auxiliary layer and the plurality of cell array trenches are lined with the conductive auxiliary layer;
removing the conductive auxiliary layer from the plurality of cell array trenches and at least partially removing the conductive auxiliary layer in the at least one connecting trench; and
forming a gate electrode structure in the plurality of cell array trenches;
wherein the field electrode structure contacts a region of the at least one connecting trench, and wherein the at least one connecting trench connects the plurality of cell array trenches. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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37. A method of making a power transistor arrangement having a transistor edge termination, the method comprising:
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providing a cell array in a semiconductor substrate including a substrate surface;
providing in the semiconductor substrate a plurality of cell array trenches and at least one edge trench which surrounds the cell array and forms the transistor edge termination, the plurality of cell array trenches being greater in width than the at least one edge trench;
applying an insulating layer to the substrate surface and in the plurality of cell array trenches and the at least one edge trench;
applying a conductive auxiliary layer to the insulating layer, wherein the at least one edge trench is filled with the conductive auxiliary layer and the plurality of cell array trenches are lined with the conductive auxiliary layer;
removing the conductive auxiliary layer from the plurality of cell array trenches and at least partially removing the conductive auxiliary layer in the at least one edge trench to substantially the level of the substrate surface, wherein removal of the conductive auxiliary layer provides exposed portions of the insulating layer;
removing the exposed portions of the insulating layer;
applying a gate insulating layer;
applying a second conductive layer to form a gate electrode structure; and
at least partially removing the second conductive layer to substantially the level as the substrate surface, thereby forming the gate electrode structure from the second conductive layer. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A power transistor arrangement comprising:
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at least one cell array formed in a semiconductor substrate;
a plurality of cell array trenches formed within the cell array in the semiconductor substrate, the plurality of cell array trenches including an outer cell array trench and a plurality of inner cell array trenches arranged parallel to one another;
a plurality of trench transistor cells formed along the inner cell array trenches;
at least one gate electrode structure insulated from the semiconductor substrate by a gate insulating layer and arranged within one of the plurality of cell array trenches;
a gate metallization, wherein at least portions of the gate metallization are arranged above the cell array and are electrically conductively connected to the gate electrode structure;
a source metallization, wherein at least portions of the source metallization are arranged above the cell array, the source metallization electrically conductively connected by a plurality of source contact trenches to source regions formed in the semiconductor substrate; and
an edge trench surrounding the cell array, the edge trench lined with an insulating layer and is filled with a conductive material. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. A power transistor arrangement comprising:
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at least one cell array formed in a semiconductor substrate;
a plurality of cell array trenches formed within the cell array in the semiconductor substrate, the plurality of cell array trenches including an outer cell array trench and a plurality of inner cell array trenches arranged parallel to one another;
a plurality of trench transistor cells formed along the inner cell array trenches;
at least one gate electrode structure insulated from the semiconductor substrate by a gate insulating layer and arranged within one of the plurality of cell array trenches;
a gate metallization, wherein at least portions of the gate metallization are arranged above the cell array and are electrically conductively connected to the gate electrode structure;
a source metallization, wherein at least portions of the source metallization are arranged above the cell array, the source metallization electrically conductively connected by a plurality of source contact trenches to source regions formed in the semiconductor substrate; and
an edge trench surrounding the cell array, the edge trench lined with an insulating layer and is filled with a conductive material, wherein at least one side of the insulating layer has a greater thickness than the thickness of the gate insulating layer.
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Specification