Device isolation structures of semiconductor devices and manufacturing methods thereof

• US 20050145980A1
• Filed: 12/30/2004
• Published: 07/07/2005
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: DSS Technology Management, Inc. (Document Security Systems, Inc.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Koh, Kwan-Ju
• Granted Patent: US 7,042,062 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence

Abstract

A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a second thermal oxide layer formed on the pad oxide layer and having a round side adjacent to an opening of the trench, and a field oxide layer filled in the trench having the first thermal oxide layer.

Claims

1. A device isolation structure of a semiconductor device comprising:

a silicon wafer;

a trench formed in the silicon wafer to have a predetermined depth;

a first thermal oxide layer formed to an inner surface of the trench;

a pad oxide layer formed on the silicon wafer;

a second thermal oxide layer formed on the pad oxide layer, having a round side adjacent to an opening of the trench; and

a field oxide layer filled in the trench having the first thermal oxide layer.

2. A device isolation structure of claim 1, wherein the second thermal oxide layer is adjacent to the opening of the trench.

3. A method for manufacturing a device isolation structure of a semiconductor device comprising:

(A) depositing a pad oxide layer and a pad nitride layer, successively;

(B) forming a first photoresist pattern for defining a device isolation region on the pad nitride layer;

(C) selectively etching the pad nitride layer using a mask of the photoresist pattern;

(D) forming a poly-silicon layer on the entire silicon wafer including the pad nitride layer;

(E) forming a second photoresist pattern on the poly-silicon layer for defining a region wider than the device isolation region defined by the first photoresist pattern;

(F) back-etching the poly-silicon layer and the silicon wafer using a mask of the second photoresist pattern and the pad nitride layer to form a first trench and a poly stringer;

(G) selectively etching the silicon wafer using a mask of the pad nitride layer to form a second trench and to maintain the poly stringer by as much as a predetermined amount to a sidewall of the pad nitride layer, at the same time;

(H) oxidizing the second trench and the remaining poly stringer to form a first thermal oxide layer and a second thermal oxide layer;

(I) depositing a field oxide layer heavily on the silicon wafer having the first thermal oxide layer and the second thermal oxide layer to fill the second trench; and

(J) polishing the field oxide layer by a chemical mechanical polishing (CMP) until a surface of the pad nitride layer are exposed, for the planarization.

4. The method of claim 3, wherein the back-etching is performed on the basis of a selective ratio of the pad nitride layer and the poly-silicon layer.

5. The method of claim 4, wherein the depth of the first trench is 20% to 30% of the depth of the second trench.

6. The method of claim 4, wherein the second trench has a depth of 4000 Å

to 10,000 Å

.

7. The method of claim 3, wherein the depth of the first trench is 20% to 30% of the depth of the second trench.

8. The method of claim 3, wherein the second trench has a depth of 4000 Å

to 1,000 Å

.

9. The method of claim 3, wherein the poly-silicon layer has a thickness of 300 Å

to 1500 Å

.

10. The method of claim 3, further comprising removing the pad nitride layer after polishing the field oxide layer.