Microdisplay packaging system

• US 20050146003A1
• Filed: 12/31/2003
• Published: 07/07/2005
• Est. Priority Date: 12/31/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: O'Connor, Michael, Ward-Dolkas, Paul C., Springett, Thomas W.
• Granted Patent: US 7,397,067 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: G02F 1/1333 Constructional arrangements; Manufacturing methodsG02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133308 Support structures for LCD panels, e.g. frames or bezels
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 2201/54 Arrangements for reducing warping-twist
• CPC Class Codes: G02F 2203/60 Temperature independent

Abstract

Some embodiments provide a microdisplay integrated circuit (IC), a substantially transparent protective cover coupled to the microdisplay IC, and a base coupled to the microdisplay IC. Thermal expansion characteristics of the base may be substantially similar to thermal expansion characteristics of the protective cover. According to some embodiments, at least one set of imaging elements is fabricated on an upper surface of a semiconductor substrate, and a base is affixed to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base.

Claims

1. A device comprising:

a microdisplay integrated circuit (IC);

a substantially transparent protective cover coupled to the microdisplay IC; and

a base coupled to the microdisplay IC,

wherein thermal expansion characteristics of the base are substantially similar to thermal expansion characteristics of the protective cover.

2. A device according to claim 1, the microdisplay IC comprising:

a semiconductor substrate; and

imaging elements,

wherein the imaging elements are disposed between the cover and the semiconductor substrate, and

wherein the semiconductor substrate is disposed between the base and the imaging elements.

3. A device according to claim 1, wherein the protective cover is composed of a first material of a first thickness, and the base is composed substantially of the first material of substantially the first thickness.

4. A device according to claim 1, further comprising:

a chip carrier coupled to the base.

5. A device according to claim 4, the chip carrier defining a recess, the base mounted within the recess.

6. A device according to claim 5, a foot of the recess having a first thickness, the first thickness substantially smaller than a thickness of the combined microdisplay IC, the cover, and the base.

7. A device according to claim 5, the chip carrier defining an opening,

wherein the protective cover extends partially into, fully into, partially through or fully through the opening.

8. A device according to claim 5, the chip carrier defining an opening,

wherein the base extends partially into, fully into, partially through or fully through the opening.

9. A device according to claim 8, further comprising:

a heat sink coupled to the base.

10. A device according to claim 5, further comprising:

a heat sink coupled to the chip carrier.

11. A device comprising:

a microdisplay integrated circuit (IC);

a substantially transparent protective cover coupled to the microdisplay IC; and

a chip carrier defining a recess, the microdisplay IC mounted within the recess.

12. A device according to claim 11, a foot of the recess having a first thickness, the first thickness substantially smaller than a thickness of the combination of the microdisplay IC and the cover.

13. A device according to claim 11, further comprising:

a heat sink coupled to the chip carrier.

14. A device according to claim 13, wherein the heat sink is coupled to a foot of the recess.

15. A device according to claim 11, further comprising:

a base coupled to the microdisplay IC,

wherein the base is mounted within the recess.

16. A device comprising:

a microdisplay integrated circuit (IC);

a substantially transparent protective cover coupled to the microdisplay IC; and

a chip carrier defining an opening,

wherein the cover extends partially into, fully into, partially through or fully through the opening.

17. A device according to claim 16, further comprising:

a base coupled to the microdisplay IC.

18. A device according to claim 17, further comprising:

a heat sink coupled to the base.

19. A device according to claim 16, wherein the chip carrier is coupled to the microdisplay IC.

20. A device according to claim 19, wherein the microdisplay IC comprises imaging elements and a bonding surface, the bonding surface comprising first conductors to carry electrical signals to the imaging elements,

wherein the chip carrier comprises second conductors to carry the electrical signals, and

wherein the first conductors contact respective ones of the second conductors.

21. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to generate substantially negligible mechanical stress between the semiconductor substrate and the base in a case that the imaging elements are operated within a range of operating temperatures.

22. A method according to claim 21, wherein affixing the base comprises:

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at at least one operating temperature of the imaging elements.

23. A method according to claim 21, wherein thermal expansion characteristics of the base are substantially to thermal expansion characteristics of the semiconductor substrate.

24. A method comprising:

fabricating at least one set of imaging elements on an upper surface of a semiconductor substrate; and

affixing a base to a lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate.

25. A method according to claim 24, wherein affixing the base comprises:

affixing the base to the lower surface of the semiconductor substrate to substantially flatten the semiconductor substrate in a case that the imaging elements are operated within a range of operating temperatures.

26. A method according to claim 24, wherein affixing the base comprises:

applying an epoxy to one or both of the base and the lower surface of the semiconductor substrate;

bringing the base and the lower surface into contact with one another while at a temperature equal to at least one operating temperature of the imaging elements; and

partially curing the epoxy at at least one operating temperature of the imaging elements.

27. A system comprising:

an Ultra High Pressure light source to emit light;

a condenser lens to condense the light;

a display device to receive the condensed light and to emit image light, the display device comprising;

a microdisplay integrated circuit (IC);

a substantially transparent protective cover coupled to the microdisplay IC; and

a base coupled to the microdisplay IC, thermal expansion characteristics of the base being substantially similar to thermal expansion characteristics of the protective cover; and

a projector lens to project the image light.

28. A system according to claim 27, wherein the display device comprises:

a chip carrier,

wherein the chip carrier defines a recess, and

wherein the base is mounted within the recess.