Memory module and method having on-board data search capabilities and processor-based system using such memory modules

• US 20050146943A1
• Filed: 02/11/2005
• Published: 07/07/2005
• Est. Priority Date: 08/28/2003
• Status: Abandoned Application

• Current Assignee: JEDDELOH, JOSEPH M.
• Original Assignee: JEDDELOH, JOSEPH M.
• Inventors: Jeddeloh, Joseph M.
• Application Number:
  US11/056,080
• Publication Number:
  US 20050146943A1
• Time in Patent Office: Days
• US Class Current: 365/189.50
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory interfaces coupled to respective memory devices, and a cross-bar switch coupling any of the link interfaces to any of the memory interfaces. Each memory interface includes a memory controller, a write buffer, a read cache, and a data mining module. The data mining module includes a search data memory that is coupled to the link interface to receive and store at least one item of search data. A comparator receives both the read data from the memory device and the search data. The comparator then compares the read data to the respective item of search data and provides a hit indication in the event of a match.

Claims

1-26. -26. (canceled)

27. A memory module, comprising:

a memory device; and

a memory hub, comprising;

a link interface for receiving memory requests for access to the memory device;

a memory device interface coupled to the link interface and to the memory device, the memory device interface coupling write memory requests and write data to the memory device, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device;

a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory device;

a search data memory coupled to the link interface to receive and store the at least one item of search data; and

a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory device, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.

28. The memory module of claim 27 wherein the memory module comprises a plurality of memory devices, and wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.

29. The memory module of claim 27 wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.

30. The memory module of claim 27 wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for each of the read requests for coupling to the memory device.

31. The memory module of claim 27 wherein the search data memory stores a plurality of the search data items, and wherein the memory hub comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.

32. The memory module of claim 27 further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.

33. The memory module of claim 27 wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.

34. The memory module of claim 33 wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.

35. The memory module of claim 27 wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.

36. The memory module of claim 27 wherein the link interface, the memory device interface, the direct memory access engine, the search data memory, and the comparator for each item of search data stored in the search data memory are fabricated as an integrated circuit on a common semiconductor substrate.

37. The memory module of claim 36 wherein the common semiconductor substrate further comprises the memory device.

38-52. -52. (canceled)

53. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a memory device; and

a memory hub, comprising;

a link interface for receiving memory requests for access to the memory device;

a memory device interface coupled to the link interface and to the memory device, the memory device interface coupling write memory requests and write data to the memory device, the memory device interface further coupling read memory requests to the memory device and coupling read data from the memory device;

a direct memory access engine coupled to the link interface, the direct memory access engine being operable to generate the read memory requests for coupling to the memory device;

a search data memory coupled to the link interface to receive and store the at least one item of search data; and

a comparator for each item of search data stored in the search data memory, each comparator being coupled to receive a respective item of search data from the search data memory and being coupled to receive the read data from the memory device, the comparator being operable to compare the read data to the respective item of search data and provide a hit indication in the event of a match.

54. The processor-based system of claim 53 wherein the memory module comprises a plurality of memory devices, and wherein the memory hub further comprises a plurality of link interfaces, a plurality of memory device interfaces coupled to a respective memory device, and a switch for selectively coupling one of the plurality of link interfaces and one of the plurality of memory device interfaces.

55. The processor-based system of claim 53 wherein an output of the comparator is coupled to the link interface to couple the hit indication to the link interface.

56. The processor-based system of claim 53 wherein the data mining module further comprises a memory device sequencer coupled to the direct memory access engine and to the memory devices, the memory device sequencer generating a set of command and address signals for each of the read requests for coupling to the memory device.

57. The processor-based system of claim 53 wherein the search data memory stores a plurality of the search data items, and wherein the memory hub comprises a plurality of comparators corresponding in number to the number of search data items stored in the search data memory.

58. The processor-based system of claim 53 further comprising a results memory coupled to an output of the comparator to store each of the hit indications generated by each of the comparators.

59. The processor-based system of claim 58 wherein the results memory is operable to store a memory device address indicative of a location in the memory devices where read data that resulted in each of the hit indications was stored.

60. The processor-based system of claim 59 wherein the results memory is further operable to store with each of the memory device addresses a corresponding item of search data that matched read stored at the respective address.

61. The processor-based system of claim 53 wherein the plurality of memory devices comprises a plurality of synchronous random access memory devices.

62. The processor-based system of claim 53 wherein the link interface, the memory device interface, the direct memory access engine, the search data memory, and the comparator for each item of search data stored in the search data memory are fabricated as an integrated circuit on a common semiconductor substrate.

63. The processor-based system of claim 62 wherein the common semiconductor substrate further comprises the memory device.

64-72. -72. (canceled)