Voltage detect mechanism

• US 20050146949A1
• Filed: 12/29/2003
• Published: 07/07/2005
• Est. Priority Date: 12/29/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Butler, Edward, Munguia, Peter R.
• Granted Patent: US 7,023,745 B2
• Time in Patent Office: Days
• US Class Current: 365/189.110
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU) and a memory device, coupled to the CPU. The memory device includes a charge pump circuit to amplify a first voltage, and a voltage detection circuit coupled to the charge pump circuit to disable the charge pump circuit if a second voltage is detected.

Claims

1. A system comprising:

a central processing unit (CPU); and

a memory device, coupled to the CPU, having;

a charge pump circuit to amplify a first voltage; and

a voltage detection circuit, coupled to the charge pump circuit, to disable the charge pump circuit if a second voltage is detected.

2. The system of claim 1 further comprising a regulator coupled to the voltage detection circuit, wherein the regulator is enabled whenever the second voltage is detected.

3. The system of claim 2 wherein the voltage detection circuit enables the charge pump circuit if the first voltage is detected at the voltage detection circuit.

4. The system of claim 3 wherein the memory device further comprises:

a memory array coupled to the charge pump circuit and the voltage detection circuit; and

control logic coupled to the regulator and the memory array.

5. The system of claim 4 wherein the charge pump circuit supplies the amplified first voltage to the memory array whenever the charge pump circuit is enabled.

6. The system of claim 4 wherein the second voltage is supplied to the memory array whenever the charge pump circuit is disabled.

7. The system of claim 4 wherein the first voltage is supplied to the control logic whenever the regulator is disabled.

8. The system of claim 4 wherein a regulated voltage is supplied to the control logic by the regulator whenever the regulator is enabled.

9. The system of claim 4 wherein the memory device further comprises an external voltage pad to receive the first and second voltages.

10. The system of claim 1 wherein the second voltage is greater than the first voltage.

11. The system of claim 1 wherein the memory device is a Dynamic Random Access Memory (DRAM).

12. The system of claim 1 wherein the memory device is a Static Random Access Memory (SRAM).

13. The system of claim 1 wherein the memory device is a Flash Memory.

14. A method comprising:

receiving a voltage at a memory device from an external source;

determining whether the received voltage is suitable to power a memory array within the memory device;

disabling a charge pump circuit if the received voltage is suitable to power the memory array; and

supplying the external voltage to the memory array.

15. The method of claim 14 further comprising:

enabling a regulator if the received voltage is suitable to power the memory array; and

supplying a regulated voltage to control logic within the memory device.

16. The method of claim 14 further comprising:

enabling the charge pump circuit if the received voltage is not suitable to power the memory array; and

supplying an amplified voltage to the memory array from the charge pump circuit.

17. The method of claim 16 further comprising:

disabling a regulator if the received voltage is not suitable to power the memory array; and

supplying the received voltage to control logic within the memory device.

18. The method of claim 16 further comprising:

amplifying the received voltage at the charge pump circuit to generate the amplified internal voltage.

19. A memory device comprising:

a memory array;

a charge pump circuit coupled to the memory array to amplify a first voltage; and

a voltage detection circuit, coupled to the charge pump circuit and the memory array, to disable the charge pump circuit if a second voltage is detected.

20. The memory device of claim 19 further comprising:

a regulator coupled to the voltage detection circuit, wherein the regulator is enabled whenever the second voltage is detected; and

control logic coupled to the regulator.

21. The memory device of claim 19 wherein the voltage detection circuit enables the charge pump circuit if the first voltage is detected at the voltage detection circuit.

22. The memory device of claim 21 wherein the charge pump circuit supplies the amplified first voltage to the memory array whenever the charge pump circuit is enabled.

23. The memory device of claim 21 wherein the second voltage is supplied to the memory array whenever the charge pump circuit is disabled.

24. The memory device of claim 19 wherein the second voltage is greater than the first voltage.

25. The memory device of claim 20 wherein the first voltage is supplied to the control logic whenever the regulator is disabled.

26. The memory device of claim 25 wherein a regulated voltage is supplied to the control logic by the regulator whenever the regulator is enabled.