Asynchronously-resettable decoder with redundancy

• US 20050146979A1
• Filed: 02/15/2005
• Published: 07/07/2005
• Est. Priority Date: 02/02/2000
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Esin Terzioglu, Morteza Cyrus Afghahi
• Inventors: Afghahi, Morteza Cyrus, Terzioglu, Esin
• Granted Patent: US 7,035,163 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits

Abstract

A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Claims

1. A decoder, comprising:

a. a synchronous portion, disposed to receive and responsive to a clocked signal;

b. an asynchronous portion, coupled with an asynchronous circuit; and

c. a feedback-resetting portion, coupled with the synchronous portion and the asynchronous portion and interposed there between, the feedback-resetting portion substantially isolating the synchronous portion from the asynchronous portion responsive to a predetermined asynchronous reset signal.

2-17. -17. (canceled)