Method of manufacturing a closed cell trench MOSFET

• US 20050148128A1
• Filed: 01/20/2005
• Published: 07/07/2005
• Est. Priority Date: 12/02/2003
• Status: Active Grant

• Current Assignee: Deva N. Pattanayak, Robert Xu
• Original Assignee: Deva N. Pattanayak, Robert Xu
• Inventors: Pattanayak, Deva N., Xu, Robert
• Granted Patent: US 7,361,558 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Embodiments of the present invention provide an improved closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The closed cell TMOSFET comprises a drain, a body region disposed above the drain region, a gate region disposed in the body region, a gate insulator region, a plurality of source regions disposed at the surface of the body region proximate to the periphery of the gate insulator region. A first portion of the gate region and the gate oxide region are formed as parallel elongated structures. A second portion of the gate region and the oxide region are formed as normal-to-parallel elongated structures. A portion of the gate and drain overlap region are selectively blocked by the body region, resulting in lower overall gate to drain capacitance.

Claims

1. A method of fabrication a closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET) comprising:

depositing a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity;

etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches;

forming a dielectric proximate said plurality of trenches;

doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches;

depositing a second semiconductor layer in said plurality of trenches;

doping a first portion of said first semiconductor layer with a second type of impurity; and

doping a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity.

2. The method according to claim 1, wherein said depositing said first semiconductor layer comprises epitaxial depositing silicon lightly doped with phosphorous.

3. The method according to claim 1, wherein said doping said first portion of said first semiconductor layer with said second type of impurity comprises implanting boron to form a body region.

4. The method according to claim 1, wherein said forming a dielectric proximate said plurality of trenches comprises oxidizing said first semiconductor layer proximate said plurality of trenches.

5. The method according to claim 1, wherein said etching said plurality of trenches is performed until the bottoms of said plurality of trenches reach a third portion of said first semiconductor layer.

6. The method according to claim 5, wherein said doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches comprises implanting boron to form a well surrounding a portion of said dielectric proximate the bottoms of said first set of said plurality of trenches.

7. The method according to claim 6, further comprising doping said first semiconductor layer proximate the bottoms of said second set of said plurality of trenches with phosphorous to form an extension from said dielectric proximate the bottoms of the second set of said plurality of trenches to said third portion of said first semiconductor layer.

8. The method according to claim 1, wherein said etching said plurality of trenches is stopped before the bottoms of said plurality of trenches reach a third portion of said first semiconductor layer.

9. The method according to claim 8, wherein said doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches comprises implanting phosphorous to form an extension from said dielectric layer proximate said bottoms of said first set of said plurality of trenches to said third portion of said first semiconductor layer.

10. The method according to claim 9, further comprising forming a buried layer doped with boron from said dielectric layer proximate said bottoms of said second set of said plurality of trenches to said third portion of said first semiconductor layer.

11. The method according to claim 1, wherein said depositing said second semiconductor layer in said plurality of trenches comprises chemical vapor depositing polysilicon heavily doped with phosphorous.

12. The method according to claim 1, wherein said doping a second portion of said first semiconductor layer proximate said dielectric with said first type of impurity comprises implanting phosphorous to form a source region.

13. The method according to claim 1, wherein said doping said first semiconductor layer proximate the bottoms of said first set of said plurality of trenches comprises implanting an impurity at a first angle such that said impurity is implanted in said first set of said plurality of trenches and not in said second set of said plurality of trenches.

14. A method of fabrication a closed cell trench metal-oxide semiconductor field effect transistor (TMOSFEET) comprising:

depositing a first portion of a first semiconductor layer upon a substrate, wherein said first semiconductor layer is doped with a first type of impurity;

doping said first portion of said first semiconductor layer, wherein a plurality of buried doped regions are formed in said first portion of said first semiconductor layer;

depositing a second portion of said first semiconductor layer upon said first portion of said first semiconductor layer;

etching a plurality of trenches in said first semiconductor layer, wherein a first set of said plurality of trenches are substantially parallel with respect to each other and aligned to said plurality of buried doped regions and wherein a second set of said plurality of trenches are substantially normal-to-parallel with respect to said first set of said plurality of trenches;

forming a dielectric proximate said plurality of trenches;

depositing a second semiconductor layer in said plurality of trenches;

doping a body region of said first semiconductor layer between said plurality of trenches with a second type of impurity; and

doping a source region of said first semiconductor layer between said plurality of trenches and said first region of said first semiconductor layer.

15. The method according to claim 14, wherein said depositing said first semiconductor layer comprises epitaxial depositing a semiconductor material lightly doped with said first type of impurity.

16. The method according to claim 15, wherein said doping said body region of said first semiconductor layer comprises implanting said second type of impurity.

17. The method according to claim 16, wherein said doping said source region of said first semiconductor layer comprises implanting said first type of impurity.

18. The method according to claim 17, wherein said substrate is doped with said first type of impurity.

19. The method according to claim 18, wherein said plurality of buried doped regions are doped with said first type of impurity.

20. The method according to claim 19, wherein said etching said plurality of trenches is performed until the bottoms of said plurality of trenches extend to said plurality of buried doped regions.