High performance strained CMOS devices
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Accused Products
Abstract
A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.
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Citations
22 Claims
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1-18. -18. (canceled)
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19. A process of forming a semiconductor structure, comprising:
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forming a structure comprised of a silicon layer, a silicon dioxide layer on the silicon layer, and a silicon nitride layer on the silicon dioxide layer;
forming a shallow trench isolation on the structure having a first shallow trench isolation side having at least one overhang configured to prevent oxidation induced stress in a first determined direction, and a second shallow trench isolation side being transverse to the first shallow trench side and being devoid of an overhang. - View Dependent Claims (20, 21, 22)
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Specification