Switched resonant ultrasonic power amplifier system

• US 20050149151A1
• Filed: 10/27/2004
• Published: 07/07/2005
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Covidien AG (Medtronic Plc)
• Original Assignee: Covidien AG (Medtronic Plc)
• Inventors: Orszulak, James H., McPherson, James W.
• Granted Patent: US 7,396,336 B2
• Time in Patent Office: Days
• US Class Current: 607/96
• CPC Class Codes: A61N 2007/0056 Beam shaping elements
• CPC Class Codes: A61N 7/00 Ultrasound therapy lithotripsy A61B17/22, A61B17/225; massage using supersonic vibration A61H23/00 ; using ultrasound for introducing media into the body A61M37/0092
• CPC Class Codes: B06B 1/0253 taken directly from the generator circuit
• CPC Class Codes: B06B 1/0261 taken from a transducer or electrode connected to the driving transducer
• CPC Class Codes: B06B 2201/76 Medical, dental
• CPC Class Codes: H10N 30/802 Drive or control circuitry or methods for piezoelectric or electrostrictive devices not otherwise provided for

Abstract

A switched resonant power amplifier system for ultrasonic transducers is disclosed. The system includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device. An output control circuit receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal, and generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal. A compensated drive circuit receives and processes the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.

Claims

1. A system for controlling an output of an ultrasonic device, the system comprising:

an amplifier receiving and processing a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device;

an output control circuit receiving and processing a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal for generating a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal; and

a compensated drive circuit receiving and processing the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.

2. The system of claim 1, wherein the feedback signal is indicative of the output of the ultrasonic device, and the output of the ultrasonic device is controlled in real time.

3. The system of claim 1, wherein the amplifier is a switched resonant power amplifier.

4. The system of claim 3, wherein the switched resonant power amplifier includes a transformer having primary and secondary windings, wherein the drive signal is coupled to the secondary winding of the transformer.

5. The system of claim 3, wherein the switched resonant power amplifier includes at least one tuning circuit having a tuned period selected to correspond to a particular resonant frequency of the driver output signal.

6. The system of claim 1, wherein the output control circuit comprises a wave shaping circuit receiving and processing the feedback signal and generating a square wave reset signal having a substantially identical frequency to the feedback signal.

7. The system of claim 6, wherein the reset signal has a waveform that is substantially 180°

out-of-phase with respect to the feedback signal.

8. The system of claim 1, wherein the output control circuit includes a compensating circuit operatively coupled to the compensated drive circuit, the compensating circuit having a phase locked loop (PLL).

9. The system of claim 8, wherein the PLL processes at least one analog signal and outputs the compensated clock signal.

10. The system of claim 6, wherein the wave shaping circuit comprises:

a zero crossing detector receiving and processing the feedback signal and generating a corresponding square wave signal; and

a comparator comparing the square wave signal to a reference signal for generating the reset signal.

11. The system of claim 8, wherein:

the output control circuit comprises a wave shaping circuit receiving and processing the feedback signal and generating a square wave reset signal having a frequency substantially identical to the feedback signal;

the compensating circuit receives and processes the reset signal for generating a compensated reference signal having substantially the same frequency as the reset signal and substantially 180°

out-of-phase with respect to the reset signal, wherein frequency and amplitude characteristics of the compensated reference signal are determined at least by the reset signal; and

wherein the PLL receives and processes first and second input signals, wherein the first input signal is the compensated reference signal, and the second input signal is the divider reference signal, and wherein the PLL processes the first and second input signals for generating the compensated clock signal.

12. The system of claim 11, wherein the PLL generates at least one of a frequency error signal and a phase error signal for compensating the compensated clock signal for at least one of phase and frequency relative to the compensated reference signal.

13. The system of claim 12, wherein the PLL includes delay circuitry for adjusting the phase of the compensated clock signal in accordance with the phase error signal.

14. The system of claim 1, wherein the compensated drive circuit includes divider circuitry for stepping down the frequency of the compensated clock signal to a selectable frequency for generating a counter output signal.

15. The system of claim 14, wherein the compensated drive circuit further includes flip-flop circuitry for splitting the counter output signal into first and second complementary square waves together forming a driver input signal.

16. The system of claim 15, wherein the respective first and second complementary square waves of the driver input signal have a frequency that is substantially one-half of the frequency of the counter output signal.

17. The system of claim 15, wherein a sample of one of at least one of the first and second complementary square waves is the divider reference signal.

18. The system of claim 15, wherein the compensated drive circuit further includes a driver for amplifying the driver input signal for generating the driver output signal, wherein the driver output signal includes first and second complementary signals.

19. The system of claim 18, wherein the amplifier includes first and second switching elements receiving the driver output signal, and the first and second complementary signals of the driver output signal are coupled to the first and second switching elements, respectively.

20. The system of claim 19, wherein the driver includes a phase delay circuit for selectively adjusting at least one of the phase relationship between the first and second complementary signals of the driver output signal and pulse width of pulses of at least one of the first and second complementary signals of the driver output signal.

21. The system of claim 20, wherein the adjusting by the phase delay circuit provides for controlling the output of the ultrasonic device for producing a pulsed output from the ultrasonic device.

22. A system for controlling an output of an ultrasonic device, the system comprising:

a switched resonant power amplifier receiving and processing a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling

the output of the ultrasonic device;

an output control circuit comprising;

a wave shaping circuit comprising;

a zero crossing detector receiving and processing a feedback signal related to the output of the ultrasonic device and generated by the ultrasonic device, the zero crossing detector generating a corresponding square wave signal; and

a comparator comparing the square wave signal to a reference signal for generating a reset signal having a substantially identical frequency to the feedback signal;

a compensating circuit comprising;

a reference timer for receiving and processing the reset signal for generating a compensated reference signal having substantially the same frequency as the reset signal and substantially 180°

out-of-phase with respect to the reset signal, wherein frequency and amplitude characteristics of the compensated reference signal are determined at least by the reset signal; and

a phase locked loop (PLL) receiving first and second input signals, wherein the first input signal is the compensated reference signal and the second input signal is a divider reference signal, and wherein the PLL processes the first and second input signals for generating a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received first and second input signals; and

a compensated drive circuit operatively coupled to the compensating circuit, the compensated drive circuit comprising;

divider circuitry for stepping down the frequency of the compensated clock signal to a selectable frequency for generating a counter output signal;

flip-flop circuitry for splitting the counter output signal into first and second complementary square waves together forming a driver input signal, wherein a sample of at least one of the first and second complementary square waves is the divider reference signal; and

a driver for amplifying the driver input signal for generating the driver output signal.

23. A system for controlling an output of an ultrasonic device, the system comprising:

an amplifier receiving and processing a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device;

an output control circuit receiving and processing a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal for generating a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal; and

a compensated drive circuit comprising;

divider circuitry for stepping down the frequency of the compensated clock signal to a selectable frequency for generating a counter output signal;

flip-flop circuitry for splitting the counter output signal into first and second complementary square waves together forming a driver input signal, wherein a sample of at least one of the first and second complementary square waves is the divider reference signal; and

a driver for amplifying the driver input signal for generating the driver output signal;

wherein the driver comprises a phase delay circuit for selectively adjusting at least one of the phase relationship between the first and second complementary signals of the driver output signal and pulse width of pulses of at least one of the first and second complementary signals of the driver output signal.