System having a plurality of integrated circuit buffer devices
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Abstract
A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device. A second plurality of signal lines are coupled to the first integrated circuit buffer device. A second integrated circuit buffer device is coupled to the second plurality of signal lines, the second integrated circuit buffer device receives the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines. A second plurality of integrated circuit memory devices are coupled to the second integrated circuit buffer device. A third plurality of signal lines are coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the master device. The third plurality of signal lines communicate information from the master device that initialize the first integrated circuit buffer device and the second integrated circuit buffer device.
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Citations
52 Claims
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1-24. -24. (canceled)
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25. A system comprising:
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a master device;
a first integrated circuit buffer device;
a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device;
a first plurality of signal lines coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines to communicate control information, address information and data from the master device to the first integrated circuit buffer device;
a second plurality of signal lines coupled to the first integrated circuit buffer device;
a second integrated circuit buffer device coupled to the second plurality of signal lines, the second integrated circuit buffer device to receive the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines; and
a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device; and
a third plurality of signal lines coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the master device, the third plurality of signal lines to communicate information from the master device, the information to initialize the first integrated circuit buffer device and the second integrated circuit buffer device. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32)
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33. A method of operation in a memory system, wherein the memory system includes a controller device coupled to a first memory module and a second memory module, wherein the first memory module includes a first integrated circuit buffer device and a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device, and the second memory module includes a second integrated circuit buffer device and a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device, the method comprising:
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the first integrated circuit buffer device receiving first control information, first address information and first data from the controller device over a first point-to-point link coupled to the first integrated circuit buffer device and the controller device;
the second integrated circuit buffer device receiving the first control information, the first address information and the first data from the first integrated circuit buffer device over a second point-to-point link coupled to the first integrated circuit buffer device and the second integrated circuit buffer device; and
the controller device providing information to initialize the first integrated circuit buffer device and the second integrated circuit buffer device. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41)
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42. A system comprising:
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a memory controller device having an interface;
a first memory module having a first integrated circuit buffer device and a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device;
a first point-to-point link coupled to the first integrated circuit buffer device and the interface of the memory controller device, the first point-to-point link to communicate control information, address information, and data from the memory controller to the first integrated circuit buffer device;
a second point-to-point link coupled to the first integrated circuit buffer device;
a second memory module having a second integrated circuit buffer device and a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device, wherein the second integrated circuit buffer device is coupled to the second point-to-point link, the second point-to-point link to communicate the control information, the address information and the data from the first integrated circuit buffer device to the second integrated circuit buffer device; and
a plurality of signal lines coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the memory controller device, the plurality of signal lines to provide signals from the memory controller device to the first integrated circuit buffer device and the second integrated circuit buffer device, the signals including information to initialize the first integrated circuit buffer device and the second integrated circuit buffer device. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51)
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52. A memory system comprising:
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a memory controller device having an interface;
a first memory module including;
a first integrated circuit buffer device;
a first integrated circuit memory device coupled to the first integrated circuit buffer device, the first integrated circuit memory device to transmit first read data to the first integrated circuit buffer device over a first channel; and
a second integrated circuit memory device coupled to the first integrated circuit buffer device, the second integrated circuit memory device to transmit second read data to the first integrated circuit buffer device over a second channel;
a first signal line coupled to the first integrated circuit buffer device and the first integrated circuit memory device, the first signal line to provide a first signal, wherein the first read data propagates to the first integrated circuit buffer device in a predetermined alignment with the first signal; and
a second signal line coupled to the first integrated circuit buffer device and the second integrated circuit memory device, the second signal line to provide a second signal, wherein the second read data propagates to the first integrated circuit buffer device in a predetermined alignment with the second signal;
a first point-to-point link having a first end coupled to the first integrated circuit buffer device and a second end coupled to the interface of the memory controller device, the first point-to-point link to communicate control information, address information, and data from the memory controller to the first integrated circuit buffer device, and the first point-to-point link to communicate the first read data and the second read data from the first integrated circuit buffer device to the interface of the memory controller device;
a second point-to-point link having a first end coupled to the first integrated circuit buffer device;
a second memory module having a second integrated circuit buffer device and a second plurality of integrated circuit memory devices coupled to the second integrated circuit buffer device, wherein the second integrated circuit buffer device is coupled to a second end of the second point-to-point link, the second point-to-point link to communicate the control information, the address information and the data from the first integrated circuit buffer device to the second integrated circuit buffer device; and
a plurality of signal lines coupled to the first integrated circuit buffer device, the second integrated circuit buffer device and the memory controller device, the plurality of signal lines to provide signals from the memory controller device to the first integrated circuit buffer device and the second integrated circuit buffer device, the signals including information to initialize the first integrated circuit buffer device and the second integrated circuit buffer device.
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Specification