Characterizing circuit performance by separating device and interconnect impact on signal delay
First Claim
1. A method for analyzing an integrated circuit (IC), the method comprising:
- measuring a first delay value from a first embedded test circuit in the IC, the first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load being formed at least in part in a first interconnect layer in the IC;
measuring a second delay value from a second embedded test circuit in the IC, wherein the second embedded test circuit is an unloaded test circuit, the second embedded test circuit comprising a second ring oscillator, the second ring oscillator being substantially similar to the first ring oscillator; and
comparing the first delay value to the second delay value.
1 Assignment
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Accused Products
Abstract
An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
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Citations
22 Claims
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1. A method for analyzing an integrated circuit (IC), the method comprising:
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measuring a first delay value from a first embedded test circuit in the IC, the first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load being formed at least in part in a first interconnect layer in the IC;
measuring a second delay value from a second embedded test circuit in the IC, wherein the second embedded test circuit is an unloaded test circuit, the second embedded test circuit comprising a second ring oscillator, the second ring oscillator being substantially similar to the first ring oscillator; and
comparing the first delay value to the second delay value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for analyzing an integrated circuit (IC), the method comprising:
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creating a first embedded test circuit in the IC for generating a first output delay, the first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load being formed in a first interconnect layer of the IC;
creating a second embedded test circuit in the IC for generating a second output delay, the second embedded test circuit comprising a second ring oscillator, the second ring oscillator being an unloaded ring oscillator, the second ring oscillator being substantially similar to the first ring oscillator;
providing a first parameter equation and a second parameter equation, the first parameter equation and the second parameter equations specifying a first Front End Of the Line (FEOL) parameter and a first Back End Of the Line (BEOL) parameter, respectively, as functions of the first output delay and the second output delay;
measuring a first measured output delay and a second measured output delay from the first embedded test circuit and the second embedded test circuit, respectively;
substituting the first measured output delay and the second measured output delay into the first parameter equation to generate a first FEOL parameter value; and
substituting the first measured output delay and the second measured output delay into the second parameter equation to generate a first BEOL parameter value. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit (IC) chip comprising an IC formed on a substrate, the IC comprising:
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a first interconnect layer;
a first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load comprising an interconnect structure formed in the first interconnect layer; and
a second embedded test circuit comprising a second ring oscillator, the second ring oscillator comprising an unloaded ring oscillator, and the second ring oscillator being substantially similar to the first ring oscillator. - View Dependent Claims (17, 18, 19, 20)
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21. A system for analyzing an integrated circuit (IC) comprising:
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means for measuring a first delay value from a first embedded test circuit in the IC, the first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load representing an interconnect path in the IC;
means for measuring a second delay value from a second embedded test circuit in the IC, wherein the second embedded test circuit is an unloaded test circuit, the second embedded test circuit comprising a second ring oscillator; and
means for comparing the first delay value to the second delay value. - View Dependent Claims (22)
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Specification