On-chip timing characterizer
First Claim
1. An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits, comprising:
- a programmable delay circuit having a signal input that receives a first input signal and an output that provides a delayed signal that is a delayed version of said first input signal, the output of said programmable delay circuit being connected to a first input of a circuit under test during timing parameter characterization;
a timing analyzer having a first input connected to the output of the programmable delay circuit during skew measurement;
a second input connected to receive a second input signal during the skew measurement, the second input signal being connected to a second input of said circuit under test during the timing parameter characterization;
a first output connected to a first control input of said programmable delay generator for controlling a delay value of the programmable delay generator; and
a second output providing a result of the skew measurement and/or timing parameter characterization;
a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of said programmable delay generator and receiving an output from said programmable delay generator for providing a value corresponding to a measured chip specific delay element timing, said characterization circuit being enabled by a control signal from said analyzer during a setup phase thereby enhancing the measurement accuracy for both skew measurement and timing parameter characterization.
1 Assignment
0 Petitions
Accused Products
Abstract
An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits providing increased accuracy and range. The measurement circuit includes a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of the programmable delay generator and receiving an output from the programmable delay generator for providing a value corresponding to the measured chip specific delay element timing, the characterization circuit being enabled by a control signal from the analyzer during a setup phase of the measurement cycle thereby enhancing the accuracy of the measurement for both skew measurement and timing parameter characterization.
15 Citations
7 Claims
-
1. An on-chip timing measurement circuit for improving skew measurement and timing parameter characterization in integrated logic circuits, comprising:
-
a programmable delay circuit having a signal input that receives a first input signal and an output that provides a delayed signal that is a delayed version of said first input signal, the output of said programmable delay circuit being connected to a first input of a circuit under test during timing parameter characterization;
a timing analyzer having a first input connected to the output of the programmable delay circuit during skew measurement;
a second input connected to receive a second input signal during the skew measurement, the second input signal being connected to a second input of said circuit under test during the timing parameter characterization;
a first output connected to a first control input of said programmable delay generator for controlling a delay value of the programmable delay generator; and
a second output providing a result of the skew measurement and/or timing parameter characterization;
a chip delay element characterization circuit for determining chip specific delay values having one output connected to a second control input of said programmable delay generator and receiving an output from said programmable delay generator for providing a value corresponding to a measured chip specific delay element timing, said characterization circuit being enabled by a control signal from said analyzer during a setup phase thereby enhancing the measurement accuracy for both skew measurement and timing parameter characterization. - View Dependent Claims (2, 3, 4)
-
-
5. An on-chip method for measuring skew and timing characteristics of integrated circuits providing increased accuracy and range, comprising the steps of:
-
providing a programmable delay to a first input signal, thereby producing a delayed signal;
connecting said delayed signal to a first input of a circuit under test in a case of timing parameter characterization, whereas connecting the delayed signal to a first input of a timing analyzer in a case of skew measurement;
supplying a second input signal to a second input of said circuit under test in the case of timing parameter characterization whereas supplying said second input signal to a second input of said analyzer in the case of skew measurement;
automatically adjusting the programmable delay using a first output of said analyzer; and
receiving a result of the skew measurement and/or timing parameter characterization from a second output of said analyzer;
characterizing chip specific delays by connecting a chain of delay elements that provides the programmable delay as a ring counter and deriving a unit delay value from an oscillation frequency of the ring counter, during a setup phase thereby enhancing the measurement accuracy for both skew measurement and timing parameter characterization. - View Dependent Claims (6)
-
-
7. An on-chip timing measurement circuit for improving skew measurement in integrated logic circuits, comprising:
-
a programmable delay circuit having a signal input that receives a first input signal, a control input, and an output that provides a delayed signal that is a delayed version of said first input signal, and a skew analyzer having a first input connected to the output of the programmable delay circuit;
a second input connected to receive a second input signal;
a first output connected to the control input of the programmable delay generator for controlling a delay value of the programmable delay generator, and a second output, the skew analyzer being structured to measure a skew between the delayed signal and the second input signal, iteratively adjust the delay value until the skew is substantially zero, and output a value on the second output that reflects a skew between the first and second input signals.
-
Specification