Hardware/software co-verification method
First Claim
1. A method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:
- (a) inputting, as a verification model, a timed software component described in a C-based language and compiling the same, inputting as a verification model a hardware component described in the C-based language and compiling the same, and linking together the compiled timed software component and the compiled hardware component;
(b) inputting a testbench and compiling the same;
(c) linking together the verification models processed in step (a) and the testbench processed in step (b);
(d) performing a simulation based on an executing program generated in step (c); and
(e) outputting a result of the simulation performed in step (d).
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Abstract
A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.
27 Citations
7 Claims
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1. A method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:
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(a) inputting, as a verification model, a timed software component described in a C-based language and compiling the same, inputting as a verification model a hardware component described in the C-based language and compiling the same, and linking together the compiled timed software component and the compiled hardware component;
(b) inputting a testbench and compiling the same;
(c) linking together the verification models processed in step (a) and the testbench processed in step (b);
(d) performing a simulation based on an executing program generated in step (c); and
(e) outputting a result of the simulation performed in step (d). - View Dependent Claims (4, 6)
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2. A method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:
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(a) inputting, as a verification model, a timed software component constructed from binary code native to the host CPU, inputting as a verification model a hardware component described in a C-based language and compiling the same, and linking together the input timed software component and the compiled hardware component;
(b) inputting a testbench and compiling the same;
(c) linking together the verification models processed in step (a) and the testbench processed in step (b);
(d) performing a simulation based on an executing program generated in step (c); and
(e) outputting a result of the simulation performed in step (d). - View Dependent Claims (5, 7)
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3. A method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted, the hardware/software co-verification method comprising the steps of:
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(a) inputting as a verification model a timed software component described in a C-based language and compiling the same, inputting as a verification model a timed software component constructed from binary code native to the host CPU and compiling the same, inputting as a verification model a hardware component described in the C-based language and compiling the same, and linking together the compiled or input timed software components and the compiled hardware component;
(b) inputting a testbench and compiling the same;
(c) linking together the verification models processed in step (a) and the testbench processed in step (b);
(d) performing a simulation based on an executing program generated in step (c); and
(e) outputting a result of the simulation performed in step (d).
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Specification