Multithread processor architecture for triggered thread switching without any cycle time loss, and without any switching program command

• US 20050149931A1
• Filed: 11/12/2004
• Published: 07/07/2005
• Est. Priority Date: 11/14/2003
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lin, Jinan, Nie, Xiaoning
• Application Number:
  US10/987,215
• Publication Number:
  US 20050149931A1
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A multithread processor according to the inventive architecture is a clocked multithread processor for data processing of threads having a standard processor root unit (1) in which threads can be switched to a different thread T₁ by means a thread switching trigger data field (11), triggered by the thread T_j which is currently to be processed by the standard processor root unit (1), without any clock cycle loss, with each program instruction I_jk for a thread T_j having a thread switching trigger data field (11) such as this.

Claims

53. A multithread processor for data processing of a plurality of threads, the multithread processor comprising:

a standard processor root unit operable to process a thread T_j, each program instruction I_jk for the thread T_j including an associated thread switching trigger data field;

a circuit operable to cause the standard processor root unit to switch, without any clock cycle loss, to process a different thread T₁ responsive to information in a first thread switching trigger data field obtained from the a particular program instruction for the thread T_j.

54. The multithread processor according to claim 53, wherein each thread is in one of a set of states, the set of states including a first state in which the thread is being executed, a second state in which the thread is ready to compute, a third state in which the thread is waiting, and a fourth state in which the thread is sleeping.

55. The multithread processor according to claim 54, further comprising an instruction fetch unit configured to fetch program instructions for the thread T_j from a program instruction memory, and wherein for each fetched program instruction, the associated thread switching trigger data field indicates whether a thread T_j is to be switched from the first state to the third state, and further indicates the number n of delayed clock cycles for which the thread T_j is to be held in the third state if the thread T_j is to be switched from the first state to the third state.

56. The multithread processor according to claim 53, further comprising an extended instruction register operable to temporarily store at least one fetched program instruction.

57. The multithread processor according to claim 56, wherein the standard processor root unit is operable to perform sequential instruction execution of the temporarily stored at least one fetched program instruction, and wherein the standard processor root unit is clocked by a clock signal having a predetermined clock cycle time.

58. The multithread processor according to claim 53, further comprising at least one context memory, each context memory configured to temporarily store a current context for a corresponding thread.

59. The multithread processor according to claim 53, wherein at least one program instruction includes data which indicates a number n of delayed clock cycles for which the thread T_j will be held in a waiting state.

67. The multithread processor according to claim 55, wherein the thread switching trigger data field for a specific program instruction is included in a program instruction which occurred a number m of clock cycles previously.

68. The multithread processor according to claim 53, wherein the thread switching trigger data field includes two or more control bits in addition to a conventional program instruction format.

72. The multithread processor according to claim 53, wherein the standard processor unit includes an instruction decoder configured to decode a program instruction, an instruction execution unit configured to execute the decoded program instruction, and a write-back unit configured to write back operation results.

73. The multithread processor according to claim 58, wherein the at least one context memory includes a program counting register configured to store a program counter, a register bank configured to store operands, and a status register configured to store status signal elements.

74. The multithread processor according to claim 58, wherein a number N of context memories is predetermined.

75. The multithread processor according to claim 58, wherein the at least one context memory comprises N context memories, each corresponding to one of the plurality of threads, each including a program counting register, a register bank, and a status register, and wherein memory contents of the program counting register, memory contents of the register bank and memory contents of the status register indicate a context of the corresponding thread.

76. The multithread processor according to claim 73, further comprising an instruction fetch unit that is operably connected to a program instruction memory in order to read a program instructions, and wherein the program counting register is operable to provide an address for the program instruction to the program instruction memory.

77. The multithread processor according to claim 53, wherein the standard processor unit is operable to provide processed data to a data bus.

79. The multithread processor according to claim 53, wherein the standard processor unit is operable to process a program instruction to be processed within a predetermined number of clock cycles.

91. The multithread processor according to claim 53, wherein the standard processor unit comprises at least a portion of one of a group consisting of a DSP processor, a protocol processor and a general purpose processor.

92. The multithread processor according to claim 53, wherein the standard processor unit includes an instruction execution unit, the instruction execution unit including at least one of a group consisting of an arithmetic logic unit (ALU) and an address generator unit (AGU).

60. A multithread processor for data processing of a plurality of threads, each thread being in one of a set of states, the set of states including a first state in which the thread is being executed, a second state in which the thread is ready to compute, a third state in which the thread is waiting, and a fourth state in which the thread is sleeping, the multithread processor comprising:

a standard processor unit operable to process a thread T_j;

a switching detector to generate a switching trigger signal responsive to a thread switching trigger data field obtained from the thread T_j, the switching trigger signal operable to cause the standard processor unit to switch to process a different thread T₁, the switching detector further operable to cause the thread T_j to switch from the first state to the third state for n delayed clock cycles based on the thread switching trigger data field, the switching detector further operable to generate a thread reactivation signal after passage of the n clock cycles;

an instruction fetch unit configured to fetch program instructions for at least the thread T_j from a program instruction memory, each fetched program instruction having an associated thread switching trigger data field.

61. The multithread processor according to claim 60, further comprising a thread monitoring unit configured to control a sequence of the program instructions to be processed by the standard processor unit for the various threads as a function of the switching trigger signal and of the thread reactivation signal, wherein, responsive to the switching trigger signal, the thread monitoring unit is operable to cause the thread T_j to switch from the first state to the third state, and to cause the thread T₁ to switch from the second state to the first state, and responsive to the thread reactivation signal, the thread monitoring unit is operable to cause the thread T_j to switch from the third state to the second state.

62. The multithread processor according to claim 61, further comprising an N×

1 multiplexer operably coupled to cause program instructions of a specific thread to be provided to the instruction fetch unit when the specific thread is in the first state, the N×

1 multiplexer being controlled by the thread monitoring unit.

63. The multithread processor according to claim 61, further comprising an N×

1 multiplexer operable to cause, under the control of the thread monitoring unit, program instructions for a specific thread which is in the second state to be provided to the instruction fetch unit when the standard processor unit becomes available to execute a thread.

64. A multithread processor according to claim 61, further comprising an N×

1 multiplexer operable to cause, under the control of the thread monitoring unit, program instructions for a specific thread to be provided to the instruction fetch unit when the standard processor unit is available to execute a thread only if the specific thread is in the second state.

65. The multithread processor according to claim 60, wherein the switching detector includes a delay circuit corresponding to the plurality of threads, and a trigger circuit operable to generate the switching trigger signal.

66. The multithread processor according to claim 65, wherein the delay circuit further comprises a delay path for each of the plurality of threads, each delay path configured to hold the corresponding thread in the third state for a specified number of clock cycles.

69. The multithread processor according to claim 60, wherein:

the thread switching trigger data field includes two or more control bits forming a first value, and

the switching trigger signal is generated when the first value is greater than zero, the switching trigger signal causing the thread T_j to switch from the first state the third state.

70. The multithread processor according to claim 66, wherein the thread switching trigger data field includes two or more control bits forming a first value, the first value defining a length of one of the delay paths.

71. The multithread processor according to claim 60, wherein the thread reactivation signal is further operable to cause the thread T_j to switch from the third state to the second state after the n clock cycles.

78. The multithread processor according to claim 61, wherein the standard processor unit is further operable to process the sequence of the program instructions using a pipeline method.

80. The multithread processor according to claim 61, wherein the thread monitoring unit and the switching detector are configured to receive event control signals.

81. The multithread processor according to claim 80, wherein the event control signals include event control signals generated internal to the multithread processor and event control signals generated external to the multithread processor.

82. The multithread processor according to claim 80, wherein the standard processor unit is further operable to generate event control signals.

83. The multithread processor according to claim 82, wherein the standard processor unit is further operable to generate an event control signal corresponding to a switching program instruction.

84. The multithread processor according to claim 83, wherein the event control signal corresponding to the switching program instruction includes a switching signal element, an n-signal element and a delay path control signal element.

85. The multithread processor according to claim 84, wherein the switching detector is operable to generate the switching trigger signal based on the switching signal element.

86. The multithread processor according to claim 84, wherein the n-signal element defines a length of a delay path for the thread T_j.

87. The multithread processor according to claims 85, wherein the switching detector further comprises an OR gate operable to generate the switching trigger signal based on inputs from the switching signal element and the thread switching trigger data field.

88. The multithread processor according to claim 84, wherein the switching detector includes an OR gate operable to control the length of the delay path based on inputs from the thread switching data field and the n-signal element.

89. The multithread processor according to claim 84, wherein the switching detector includes an AND gate operably coupled to receive at least a portion of the thread switching data field and an inverse of the delay path control signal element.

90. The multithread processor according to claim 80, wherein the event control signals are produced by external assemblies.

93. The multithread processor according to claim 80, wherein the thread monitoring unit is configured to drive one or more switching networks as a function of the event control signals.

94. A method for switching threads T of a clocked multithread processor, the multithread processor including a standard processor unit, the method comprising:

processing a thread T_j in the standard processor unit; and

switching the standard processor unit from processing the thread T_j to another thread T₁, said switching responsive to reception of a first thread switching trigger data field, wherein each program instruction I_jk for a thread T_j includes an associated thread switching trigger data field.

1. -52. (canceled)

95. The method according to claim 94, further comprising the step of

fetching each program instructions I_jk for the thread T_j from a program instruction memory, and wherein the step of switching further comprises, switching the thread T_j from an executing state to a waiting state responsive to the first thread switching trigger data field, and holding the thread T_j in the waiting state for a number of clock cycles, the number of clock cycles indicated in the first thread switching trigger data field.

96. The method according to claim 94, further comprising temporarily storing at least one fetched program instruction in an extended instruction register.

97. The method according to claim 96, further comprising a step of sequentially executing in the standard processor unit the temporarily stored program instructions, wherein the standard processor unit is clocked by a clock signal with a predetermined clock cycle time.

98. The method according to claim 94, further comprising a step of storing two or more sets of context information, each set of context information corresponding to a thread.

99. The method according to claim 95, further comprising the steps of:

generating a switching trigger signal in a switching detector of the multithread processor responsive to the thread switching trigger data field,

generating a thread reactivation signal after the thread T_j is in the waiting state for the number of clock cycles.

100. The method according to claim 99, wherein the sequence of the program instructions to be processed by the standard processor unit is controlled by a thread monitoring unit, which operates as a function of the switching trigger signal and of the thread reactivation signals such that switching takes place between threads without any clock cycle loss by the switching trigger signal.