Accelerator for multi-processing system and method
First Claim
1. A processing system, comprising:
- a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching; and
a hardware concurrency engine coupled to the plurality of processors, the concurrency engine capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors.
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Accused Products
Abstract
A processing system includes a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching. The processing system also includes a hardware concurrency engine coupled to the plurality of processors. The concurrency engine is capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. The concurrency primitives could represent objects, and the processors may be capable of using the objects by reading from and/or writing to addresses in an address space associated with the concurrency engine. Each address may encode an object index identifying one of the objects, an object type identifying a type associated with the identified object, and an operation type identifying a requested operation involving the identified object.
97 Citations
30 Claims
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1. A processing system, comprising:
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a plurality of processors capable of executing a plurality of threads and supporting at least one of hardware context switching and software context switching; and
a hardware concurrency engine coupled to the plurality of processors, the concurrency engine capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method, comprising:
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executing a plurality of threads using a plurality of processors; and
managing a plurality of concurrency primitives that coordinate execution of the threads by the processors using a hardware concurrency engine. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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21. A concurrency engine capable of managing a plurality of concurrency primitives that coordinate execution of threads by a plurality of processors, comprising:
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a command decoder capable of decoding requests from the processors;
a command processor capable of executing operations associated with the decoded requests;
a response formatter capable of encoding results from the execution of the operations; and
a memory capable of storing information associated with a plurality of objects representing the concurrency primitives, each operation executed by the command processor involving at least one of the objects, each request from the processors comprising at least one of a read operation and a write operation involving an address in an address space associated with the concurrency engine, the address encoding an identification of one of the objects and a requested operation. - View Dependent Claims (22, 23)
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24. An apparatus, comprising:
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at least one of;
an input device and an interface to the input device, the input device capable of providing input data;
at least one of;
an output device and an interface to the output device, the output device capable of receiving output data; and
a processing system capable of receiving the input data and generating the output data, the processing system comprising;
a plurality of processors capable of executing a plurality of threads; and
a hardware concurrency engine coupled to the plurality of processors, the concurrency engine capable of managing a plurality of concurrency primitives that coordinate execution of the threads by the processors. - View Dependent Claims (25, 26, 27, 28)
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29. A processor, comprising:
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an instruction set supporting a plurality of instructions for execution;
an embedded memory capable of storing instructions to be executed, the instructions to be executed implementing at least one thread; and
a hardware concurrency engine capable of managing a plurality of concurrency primitives that coordinate execution of a plurality of threads by the processor and at least one additional processor. - View Dependent Claims (30)
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Specification