Increasing readout speed in CMOS APS sensors through block readout
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Abstract
A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided with block signaling. Accordingly, only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines. Block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high-speed imaging applications.
44 Citations
44 Claims
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1-23. -23. (canceled)
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24. An image sensor, comprising:
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a pixel array comprising a plurality of pixels, organized into N rows and M columns, wherein N and M are positive integers;
M output circuits, each of said m output circuits for respectively outputting signals from M pixels of a selected row;
wherein said M output circuits are organized into b blocks, b being a positive integer, each of said b blocks comprising;
k of said M output circuits, wherein k is a positive integer such that k=M/B;
a block output line, coupled to said k output circuits of a respective block;
a master output line;
a selection circuit, for coupling only one of said B blocks to said master output line at a time. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31)
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32. A system, comprising:
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a processor;
an image sensor, coupled to said processing, said image sensor, comprising;
a pixel array comprising a plurality of pixels, organized into N rows and M columns, wherein N and M are positive integers;
M output circuits, each of said M output circuits for respectively outputting signals from M pixels of a selected row;
wherein said M output circuits are organized into B blocks, B being a positive integer, each of said B blocks comprising;
k of said M output circuits, wherein k is a positive integer such that k=M/B;
a block output line, coupled to said k output circuits of a respective block;
a master output line;
a selection circuit, for coupling only one of said B blocks to said master output line at a time. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39)
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40. A method reading out pixels signals of a selected row in an imager having pixels arranged in N rows by M columns through M output circuits, the method comprising:
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(a) organizing said M output circuits into B groups each having k output circuits;
(b) selecting only one of said B groups by coupling a selected group to an output node; and
(c) reading out pixel signals from each of said k output circuits in the selected group;
wherein M, B, and k are integers and B is equal to M/k. - View Dependent Claims (41, 42, 43, 44)
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Specification