ISOLATION STRUCTURE FOR TRENCH CAPACITORS AND FABRICATION METHOD THEREOF

• US 20050151182A1
• Filed: 01/13/2004
• Published: 07/14/2005
• Est. Priority Date: 01/13/2004
• Status: Abandoned Application

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Chen, Yi-Nan, Hsu, Ping, Lu, Li-Han
• Application Number:
  US10/707,805
• Publication Number:
  US 20050151182A1
• Time in Patent Office: Days
• US Class Current: 257/301
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

An isolation structure of a trench capacitor of DRAM has a first isolation portion covering the trench capacitor and filling a top opening of the deep trench and a second isolation portion directly contacting the first isolation potion and surrounding the deep trench without overlapping the deep trench. The thickness of the second isolation portion is larger than the thickness of the first isolation portion.

Claims

1. A isolation structure of a trench capacitor, the trench capacitor being disposed in a deep trench of a substrate and comprising a conductive layer in the deep trench and a collar oxide layer disposed on a surface of a sidewall of the deep trench, the isolation structure comprising:

a first isolation portion covering the conductive layer and filling a top opening of the deep trench, the first isolation portion having a first thickness; and

a second isolation portion directly contacting the first isolation portion and surrounding the deep trench without overlapping the deep trench, the second isolation portion having a second thickness larger than the first thickness.

2. The isolation structure of claim 1, wherein the second isolation portion is disposed by a side of the collar oxide layer, near the conductive layer and the collar oxide layer without being located on the conductive layer and the collar oxide layer.

3. The isolation structure of claim 1, wherein a bottom of the second isolation portion is lower than a top of the collar oxide layer.

4. The isolation structure of claim 1 further comprising an isolation liner disposed between the first isolation portion and the conductive layer, the second isolation portion and the conductive layer, and the second isolation portion and the collar oxide layer.

5. The isolation structure of claim 4, wherein the isolation liner comprises a nitride liner.

6. The isolation structure of claim 4, wherein the isolation liner comprises an oxide liner.

7. The isolation structure of claim 1, wherein the first isolation portion and the second isolation portion are oxide layers.

8. The isolation structure of claim 1, wherein the first isolation portion and the second isolation portion are oxide layers formed by a high density plasma chemical vapor deposition (HDPCVD) process.

19. The isolation structure of claim 1, wherein the first isolation portion is directly positioned on and contacts the trench capacitor.

9. A method of self-aligned fabricating an isolation structure of a trench capacitor, wherein the trench capacitor is disposed in a deep trench of a substrate having a pad layer thereon, the trench capacitor comprising:

a conductive layer filled in the deep trench, wherein a top surface of the conductive layer and a sidewall of the pad layer define a recess; and

a collar oxide layer disposed on a surface of a sidewall of the deep trench;

the method comprising;

forming a mask layer and a dielectric layer in sequence on the substrate and a surface of the recess;

forming a photoresist layer on the dielectric layer, the photoresist layer having an opening that defines a shallow trench;

etching the dielectric layer, the mask layer, and the pad layer through the opening until the substrate is exposed; and

etching the substrate by taking the residual mask layer as a hard mask until a surface of the exposed substrate is lower than a top of the collar oxide layer, wherein the conductive layer and the collar oxide layer remain intact.

10. The method of claim 9 further comprising:

removing the photoresist layer, the dielectric layer, and the mask layer so as to form the shallow trench; and

filling the shallow trench with an isolation material.

11. The method of claim 10 further comprising performing an oxidation process after forming the shallow trench so as to form a oxide liner on a bottom and a sidewall of the shallow trench.

12. The method of claim 11 further comprising forming a nitride liner on the bottom and the sidewall of the shallow trench after forming the oxide liner.

13. The method of claim 10, wherein the isolation material comprises silicon oxide.

14. The method of claim 13, wherein filling the shallow trench with silicon oxide comprises:

performing a HDPCVD process to deposit a silicon oxide layer on the substrate; and

performing a chemical-mechanical polishing (CMP) process so that a surface of the silicon oxide layer is approximately coplanar with a surface of the pad layer.

15. The method of claim 9, wherein the mask layer comprises silicon nitride.

16. The method of claim 9, wherein the dielectric layer comprises borosilicate glass (BSG).

17. The method of claim 16 further comprising performing a CMP process after depositing the BSG layer.

18. The method of claim 9 further comprising depositing an anti-reflection coating (ARC) on the dielectric layer.