Ultra-high capacitance device based on nanostructures

• US 20050151261A1
• Filed: 01/26/2005
• Published: 07/14/2005
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Sarah E. Kim, Scot A. Kellar
• Original Assignee: Sarah E. Kim, Scot A. Kellar
• Inventors: Kim, Sarah E., Kellar, Scot A.
• Granted Patent: US 7,091,084 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2213/16 Memory cell being a nanotube, e.g. suspended nanotube
• CPC Class Codes: G11C 2213/81 Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/33 Thin- or thick-film capacitors thin- or thick-film circuits H01L27/00; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor H01L28/40
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: Y10S 977/70 Nanostructure
• CPC Class Codes: Y10S 977/72 On an electrically conducting, semi-conducting, or semi-insulating substrate
• CPC Class Codes: Y10S 977/721 On a silicon substrate
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate
• CPC Class Codes: Y10S 977/902 Specified use of nanostructure
• CPC Class Codes: Y10S 977/963 Miscellaneous
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Abstract

The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Claims

1. A method comprising:

providing a substrate;

forming a lower insulator over said substrate;

forming a lower conductor over said lower insulator;

forming a conducting nanostructure over said lower conductor, said conducting nanostructure being discontinuous;

forming a thin dielectric over said conducting nanostructure, said thin dielectric being conformal over said conducting nanostructure and said lower conductor;

forming an upper conductor over said thin dielectric; and

forming an upper insulator over said upper conductor.

2. The method of claim 1 wherein said conducting nanostructure is formed by self-assembly.

3. The method of claim 1 wherein said thin dielectric is formed by Atomic Layer Deposition (ALD).

4. The method of claim 1 wherein said conducting nanostructure is formed by Chemical Vapor Deposition (CVD).

5. The method of claim 1 wherein said conducting nanostructure is formed selectively.

6. The method of claim 1 wherein said conducting nanostructure is formed non-selectively.

7-21. -21. (canceled)