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Node contact structures in semiconductor devices and methods of fabricating the same

  • US 20050151276A1
  • Filed: 01/11/2005
  • Published: 07/14/2005
  • Est. Priority Date: 01/12/2004
  • Status: Active Grant
First Claim
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1. A static random-access memory (SRAM) device, comprising:

  • a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;

    an insulating layer on the bulk MOS transistor;

    a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor; and

    a multi-layer plug comprising a semiconductor plug extending through at least a portion of the insulating layer and directly on the source/drain region of the bulk MOS transistor, and a metal plug extending through at least a portion of the insulating layer and directly on the source/drain region of the thin-film transistor and the semiconductor plug.

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