Node contact structures in semiconductor devices and methods of fabricating the same

• US 20050151276A1
• Filed: 01/11/2005
• Published: 07/14/2005
• Est. Priority Date: 01/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Soon-Moon, Jang, Jae-Hoon, Hwang, Byung-Jun, Kwak, Kun-Ho
• Granted Patent: US 7,521,715 B2
• Time in Patent Office: Days
• US Class Current: 257/427
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

Claims

1. A static random-access memory (SRAM) device, comprising:

a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;

an insulating layer on the bulk MOS transistor;

a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor; and

a multi-layer plug comprising a semiconductor plug extending through at least a portion of the insulating layer and directly on the source/drain region of the bulk MOS transistor, and a metal plug extending through at least a portion of the insulating layer and directly on the source/drain region of the thin-film transistor and the semiconductor plug.

2. The device of claim 1, wherein the semiconductor plug and the source/drain region of the bulk MOS transistor comprise a same conductivity type, and wherein the source/drain region of the bulk MOS transistor and the source/drain region of the thin-film transistor comprise different conductivity types.

3. The device of claim 2, wherein the semiconductor plug and the source/drain region of the bulk MOS transistor comprise an n-type conductivity, and wherein the source drain region of the thin-film transistor comprises a p-type conductivity.

4. The device of claim 1, wherein the metal plug is directly on the source/drain region of the bulk MOS transistor and at least one sidewall of the semiconductor plug.

5. The device of claim 4, wherein the semiconductor plug comprises an intrinsic semiconductor and/or a different conductivity type than the source/drain region of the bulk MOS transistor.

6. The device of claim 5, wherein the semiconductor plug comprises a p-type conductivity, and wherein the source/drain region of the bulk MOS transistor comprises an n-type conductivity.

7. The device of claim 4, wherein the semiconductor plug is directly on the source/drain region of the thin-film transistor.

8. The device of claim 1, wherein the bulk MOS transistor is an n-channel metal oxide semiconductor (NMOS) transistor, and the thin film MOS transistor is a p-channel metal oxide semiconductor (PMOS) transistor.

9. The device of claim 1, wherein the thin-film transistor is a first thin-film transistor, and further comprising:

a second thin-film transistor on the insulating layer adjacent the first thin-film transistor,

wherein the metal plug is directly on a gate electrode of the second thin-film transistor.

10. The device of claim 9, wherein the bulk MOS transistor is a first bulk MOS transistor, wherein the metal plug is a first metal plug, and further comprising:

a second bulk MOS transistor on the substrate adjacent the first bulk MOS transistor; and

a second metal plug extending through at least a portion of the insulating layer and directly on the gate electrode of the second thin-film transistor and a gate electrode of the second bulk MOS transistor.

11. The device of claim 10, wherein the gate electrode of the second bulk MOS transistor is an n-type polysilicon pattern, and wherein the gate electrode of the second thin-film transistor is a p-type polysilicon pattern.

12. The device of claim 9, wherein the bulk MOS transistor is a driver transistor, wherein the first thin-film transistor is a load transistor, and wherein the second thin-film transistor is a transfer transistor for the SRAM device.

13. The device of claim 12, wherein a word line is connected to the gate electrode of the second thin-film transistor.

14. The device of claim 12, wherein a bit line is connected to a source/drain region of the second thin-film transistor.

15. The device of claim 1, wherein the insulating layer on the bulk MOS transistor is a first insulating layer, and further comprising:

a second insulating layer on the thin-film transistor,

wherein the metal plug extends through the second insulating layer.

16. The device of claim 1, wherein the thin-film transistor includes a body portion having a single crystalline silicon structure.

17. The device of claim 9, wherein the body portion of the thin-film transistor is formed by a solid phase epitaxial process and has a same crystalline structure as the semiconductor plug.

18. The device of claim 1, wherein the metal plug comprises a tungsten plug.

19. The device of claim 1, wherein the metal plug comprises a tungsten plug and barrier metal layer surrounding the tungsten plug.

20. A method of forming a semiconductor device, comprising:

forming a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;

forming an insulating layer on the bulk MOS transistor;

forming a semiconductor plug directly on a source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer;

forming a thin-film transistor having a source drain region therein on the insulating layer above the bulk MOS transistor; and

forming a metal plug directly on the semiconductor plug and the source/drain region of the thin-film transistor and extending through at least a portion of the insulating layer.

21. The method of claim 20, wherein the semiconductor plug and the source/drain region of the bulk MOS transistor are formed to have a same conductivity type, and wherein the source/drain region of the bulk MOS transistor and the source/drain region of the thin-film transistor are formed to have different conductivity types.

22. The method of claim 20, wherein forming the metal plug further comprises:

forming the metal plug directly on the source/drain region of the bulk MOS transistor and at least one sidewall of the semiconductor plug.

23. The method of claim 22, wherein the semiconductor plug is formed of an intrinsic semiconductor and/or a layer having a different conductivity type than the source/drain region of the bulk MOS transistor.

24. The method of claim 22, wherein forming the thin-film transistor comprises:

forming the source/drain region of the thin-film transistor directly on the semiconductor plug.

25. The method of claim 20, wherein the thin-film transistor is a first thin-film transistor, wherein the bulk MOS transistor is a first bulk MOS transistor, wherein the metal plug is a first metal plug, and further comprising:

forming a second thin-film transistor on the insulating layer adjacent the first thin-film transistor, the second thin-film transistor having a gate electrode directly on the first metal plug;

forming a second bulk MOS transistor having a gate electrode on the substrate adjacent the first bulk MOS transistor; and

forming a second metal plug extending through at least a portion of the insulating layer and directly on the gate electrode of the second thin-film transistor and a gate electrode of the second bulk MOS transistor.

26. The method of claim 20, wherein forming a thin-film transistor comprises:

forming a conductive layer pattern on the insulating layer; and

performing a solid phase epitaxial (SPE) process on the conductive layer pattern to form a thin-film transistor body pattern having a single crystalline structure.

27. The method of claim 26, wherein the solid phase epitaxial process is performed at a temperature of about 500°

C. to about 800°

C. using the semiconductor plug as a seed layer.

28. The method of claim 26, wherein the semiconductor plug and the thin-film transistor body pattern are formed of single crystalline silicon.

29. An interconnection structure in a semiconductor device, comprising:

an insulating layer on an active region of a semiconductor substrate;

a conductive layer pattern on the insulating layer; and

a multi-layer plug comprising a semiconductor plug directly on the active region and extending through at least a portion of the insulating layer, and a metal plug directly on the semiconductor plug and the conductive layer pattern and extending through at least a portion of the insulating layer.

30. The interconnection structure of claim 29, wherein the semiconductor plug and the active region comprise a same conductivity type, and wherein the active region and the conductive layer pattern comprise different conductivity types.

31. The interconnection structure of claim 30, wherein the semiconductor plug and the active region comprise an n-type conductivity, and wherein at least a portion of the conductive layer pattern comprises a p-type conductivity.

32. The interconnection structure of claim 29, wherein the metal plug is directly on the active region and at least one sidewall of the semiconductor plug.

33. The interconnection structure of claim 32, wherein the semiconductor plug comprises an intrinsic semiconductor and/or a different conductivity type than the active region.

34. The interconnection structure of claim 33, wherein the semiconductor plug comprises a p-type conductivity, and wherein the active region comprises an n-type conductivity.

35. The device of claim 32, wherein the semiconductor plug is directly on the conductive layer pattern.

36. The device of claim 35, wherein the semiconductor plug is directly on a bottom surface of the conductive layer pattern, and wherein the metal plug is directly on a sidewall of the semiconductor plug and an end portion of the conductive layer pattern.

37. The interconnection structure of claim 29, wherein the metal plug passes through a portion of the conductive layer pattern, and the semiconductor plug extends between the metal plug and the active region.

38. The interconnection structure of claim 29, wherein the conductive layer pattern is a first conductive layer pattern, and further comprising:

a second conductive layer pattern on the insulating layer adjacent the first conductive layer pattern and directly on the metal plug.

39. The interconnection structure of claim 29, wherein the conductive layer pattern and the semiconductor plug comprise single crystalline silicon.

40. The interconnection structure of claim 29, wherein the metal plug is a metal layer having ohmic contact with both an n-type semiconductor and a p-type semiconductor.

41-50. -50. (canceled)