Node contact structures in semiconductor devices and methods of fabricating the same
First Claim
1. A static random-access memory (SRAM) device, comprising:
- a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;
an insulating layer on the bulk MOS transistor;
a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor; and
a multi-layer plug comprising a semiconductor plug extending through at least a portion of the insulating layer and directly on the source/drain region of the bulk MOS transistor, and a metal plug extending through at least a portion of the insulating layer and directly on the source/drain region of the thin-film transistor and the semiconductor plug.
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Accused Products
Abstract
A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.
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Citations
41 Claims
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1. A static random-access memory (SRAM) device, comprising:
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a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;
an insulating layer on the bulk MOS transistor;
a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor; and
a multi-layer plug comprising a semiconductor plug extending through at least a portion of the insulating layer and directly on the source/drain region of the bulk MOS transistor, and a metal plug extending through at least a portion of the insulating layer and directly on the source/drain region of the thin-film transistor and the semiconductor plug. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of forming a semiconductor device, comprising:
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forming a bulk MOS transistor on a semiconductor substrate having a source/drain region therein;
forming an insulating layer on the bulk MOS transistor;
forming a semiconductor plug directly on a source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer;
forming a thin-film transistor having a source drain region therein on the insulating layer above the bulk MOS transistor; and
forming a metal plug directly on the semiconductor plug and the source/drain region of the thin-film transistor and extending through at least a portion of the insulating layer. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. An interconnection structure in a semiconductor device, comprising:
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an insulating layer on an active region of a semiconductor substrate;
a conductive layer pattern on the insulating layer; and
a multi-layer plug comprising a semiconductor plug directly on the active region and extending through at least a portion of the insulating layer, and a metal plug directly on the semiconductor plug and the conductive layer pattern and extending through at least a portion of the insulating layer. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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41-50. -50. (canceled)
Specification