Integrated circuit with tamper detection circuit

• US 20050151777A1
• Filed: 10/29/2004
• Published: 07/14/2005
• Est. Priority Date: 07/15/1997
• Status: Active Grant

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Granted Patent: US 7,193,482 B2
• Time in Patent Office: Days
• US Class Current: 347/19
• CPC Class Codes: B41J 11/0005 Curl smoothing, i.e. smoothing down corrugated printing material, e.g. by pressing means acting on wrinkled printing material
• CPC Class Codes: B41J 15/044 Cassettes or cartridges containing continuous copy material, tape, for setting into printing devices
• CPC Class Codes: B41J 2/01 Ink jet
• CPC Class Codes: B41J 2/14 Structure thereof only for on-demand ink jet heads
• CPC Class Codes: B41J 2/14427 Structure of ink jet print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/16 Production of nozzles
• CPC Class Codes: B41J 2/1623 bonding and adhesion
• CPC Class Codes: B41J 2/1626 etching
• CPC Class Codes: B41J 2/1628 dry etching
• CPC Class Codes: B41J 2/1629 wet etching
• CPC Class Codes: B41J 2/1631 photolithography
• CPC Class Codes: B41J 2/1632 machining
• CPC Class Codes: B41J 2/1635 dividing the wafer into individual chips
• CPC Class Codes: B41J 2/1637 molding
• CPC Class Codes: B41J 2/1642 thin film formation by CVD [chemical vapor deposition]
• CPC Class Codes: B41J 2/1645 thin film formation by spincoating
• CPC Class Codes: B41J 2/1646 thin film formation by sputtering
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17503 Ink cartridges
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17526 : Electrical contacts to the cartridge
• CPC Class Codes: B41J 2/17546 : electronically
• CPC Class Codes: B41J 2/17553 : Outer structure
• CPC Class Codes: B41J 2/17596 : Ink pumps, ink valves
• CPC Class Codes: B41J 2002/041 : Electromagnetic transducer
• CPC Class Codes: B41J 2202/21 : Line printing
• CPC Class Codes: B41J 29/393 : Devices for controlling or analysing the entire machine ; Controlling or analysing mechanical parameters involving printing of test patterns
• CPC Class Codes: B41J 3/44 : Typewriters or selective printing mechanisms having dual functions or combined with, or coupled to, apparatus performing other functions
• CPC Class Codes: B82Y 30/00 : Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G06F 21/79 : in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 21/86 : Secure or tamper-resistant housings
• CPC Class Codes: G06F 2221/2129 : Authenticate client device independently of the user
• CPC Class Codes: G06K 1/121 : by printing code marks applying code marks to labels B65C9/46; marking or coding completed packages B65B61/26
• CPC Class Codes: G06K 19/06 : characterised by the kind of the digital marking, e.g. shape, nature, code
• CPC Class Codes: G06K 19/06037 : multi-dimensional coding
• CPC Class Codes: G06K 19/06046 : Constructional details
• CPC Class Codes: G06K 19/073 : Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 7/14 : using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence
• CPC Class Codes: G06K 7/1417 : 2D bar codes
• CPC Class Codes: G11C 11/56 : using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: H01L 23/576 : using active circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03B 29/00 : Generation of noise currents and voltages gasfilled discharge tubes with solid cathode specially adapted as noise generators H01J17/005
• CPC Class Codes: H04N 1/00127 : Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture
• CPC Class Codes: H04N 1/00326 : with a data reading, recognizing or recording apparatus, e.g. with a bar-code apparatus arrangements for the associated working of recording or reproducing apparatus with related apparatus G11B31/00
• CPC Class Codes: H04N 1/0044 : for image preview or review, e.g. to help the user position a sheet
• CPC Class Codes: H04N 1/00965 : using a plug-in memory module, e.g. memory card, memory stick
• CPC Class Codes: H04N 1/2112 : using still video cameras
• CPC Class Codes: H04N 1/2154 : the still video camera incorporating a hardcopy reproducing device, e.g. a printer
• CPC Class Codes: H04N 1/32133 : on the same paper sheet, e.g. a facsimile page header
• CPC Class Codes: H04N 2101/00 : Still video cameras
• CPC Class Codes: H04N 2201/0008 : Connection or combination of a still picture apparatus with another apparatus
• CPC Class Codes: H04N 2201/3222 : of processing required or performed, e.g. forwarding, urgent or confidential handling
• CPC Class Codes: H04N 2201/3261 : of multimedia information, e.g. a sound signal
• CPC Class Codes: H04N 2201/3264 : of sound signals
• CPC Class Codes: H04N 2201/3269 : of machine readable codes or marks, e.g. bar codes or glyphs
• CPC Class Codes: H04N 2201/3276 : of a customised additional information profile, e.g. a profile specific to a user ID
• CPC Class Codes: H04N 2201/328 : Processing of the additional information
• CPC Class Codes: H04N 23/00 : Cameras or camera modules comprising electronic image sensors; Control thereof
• CPC Class Codes: H04N 5/2628 : Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation

Abstract

A tamper detection circuit for an integrated circuit includes a pseudo-random generator. A first line is connected to the output of the generator and a second line is connected in parallel via an inverter. A number of XOR gates are coupled to the first and second lines at locations along their length. Output from the XOR gates enables various general operational circuits of the integrated circuit. In the event of one of the lines being cut or otherwise tampered with then the output from the XOR gates will indicate a tamper state. The general operational circuits respond by either resetting or deleting critical data from memory such as the integrated circuit'"'"'s authentication key. In a preferred version a number of trigger transistors connected to ground are inserted into the paths of the first line and the second line. A physical attack upon the integrated circuit causes a nearby trigger transistor to pull its attached line to ground thereby causing the output of local XOR gates to indicate a tamper state.

Claims

1. An integrated circuit having a tamper detection circuit including:

a noise generator circuit;

a first line connected to the noise generator circuit; and

a second line connected to the noise generator circuit by an inverter;

wherein operation of one or more general circuits of the integrated circuit is dependent upon a logical combination of signals on the first line and the second line.

2. An integrated circuit according to claim 1, wherein the noise generator circuit comprises a pseudo-random bit generator.

3. An integrated circuit according to claim 2, wherein the pseudo-random bit generator is clocked at high speed relative to other circuitry of the integrated circuit.

4. An integrated circuit according to claim 1, wherein the logical combination of signals on the first line and the second line is implemented by one or more XOR gates coupled to the first line and the second line.

5. An integrated circuit according to claim 4, wherein the first line and the second line are located in a layer vertically distanced from a layer containing general operational circuitry of the integrated circuit.

6. An integrated circuit according to claim 4, wherein the one or more XOR gates comprise a plurality of XOR gates situated at a number of locations along said lines.

7. An integrated circuit according to claim 5, wherein the first line and the second line passes over the random bit generator.

8. An integrated circuit according to claim 1, wherein the one or more general circuits of the integrated circuit include memory circuits or key manipulation circuits.

9. An integrated circuit according to claim 1, wherein a number of triggers are attached to one or more of the first line and the second line, each of the triggers being configured to alter the voltage on the first line or the second line to which it is attached in response to a physical attack on the integrated circuit.

10. An integrated circuit according to claim 9, wherein the triggers comprise a number of transistors connected to ground.

11. An integrated circuit according to claim 9, wherein one or more of the general circuits is reset in response to a particular logical combination of signals on the first and second lines.

12. An integrated circuit according to claim 9, wherein one of the general circuits comprises a memory circuit containing an authentication key and wherein the memory circuit erases the authentication key in response to a particular logical combination of the signals on the first and second line.

13. An integrated circuit of a type including a number of general operational circuits and a tamper detection circuit to which said general operational circuits are responsive, the tamper detection circuit including:

a pseudo random bit generator clocked at high speed relative to other circuitry of the integrated circuit;

a first line connected to the random bit source and disposed in a layer vertically displaced relative to a layer containing the general operational circuits; and

a second line connected to the random bit source and disposed in a layer vertically displaced relative to the layer containing the general operational circuits;

a number of XOR gates coupled at locations along the first line and the second line;

a plurality of triggers attached to the first line and to the second line each of the triggers being configured to alter the voltage on the first line or the second line to which it is attached in response to a physical attack on the integrated circuit.