Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same

• US 20050152210A1
• Filed: 12/23/2004
• Published: 07/14/2005
• Est. Priority Date: 12/24/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Youn-Sik, Hwang, Sang-Joon
• Granted Patent: US 7,133,324 B2
• Time in Patent Office: Days
• US Class Current: 365/233.100
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.

Claims

1. A synchronous dynamic random access memory device for both DDR1 and DDR2 mode operations, comprising:

a mode selection circuit configured to generate a first mode selection signal that activates a DDR1 mode operation and a second mode selection signal that activates a DDR2 mode operation;

a row decoder configure to decode a row address;

a column decoder configured to select two global data lines for one unit data input/output in response to the first mode selection signal, and configured to select four global data lines for said one unit data input/output in response to the second mode selection signal;

a core section configured to receive data from the two global data lines and output the data to the two global data lines in response to the first mode selection signal, and configured to receive the data from the four global data lines and output the data to the four global data lines in response to the second mode selection signal; and

an input and output control circuit configured to prefetch two bits data in response to the first mode selection signal to provide the two bits data to the core section, configure to output the two bits data received from the core section in response to the first mode selection signal, configured to prefetch four bits data in response to the second mode selection signal to provide the four bits data to the core section, and configured to output the four bits data received from the core section in response to the second mode selection signal.

2. A column address latch including:

an address sampling circuit configured to sample an input column address synchronized with an internal clock based on an internal write command or an internal read command;

an address transfer circuit configured to transfer the sampled input column address; and

a mode selection circuit configured to determine a transfer path based on the first and second mode selection signals.

3. A column decoder comprising:

a first column decoding block configured to decode n column addresses to activate at least one first column selection line of at least 2ⁿ first column selection lines, the at least one first column selection line corresponding to the column address decoded by the first column decoding block;

a second column decoding block configured to decode the n column addresses to activate at least one second column selection line of at least 2ⁿ second column selection lines, the at least one second column selection line corresponding to the column address decoded by the second column decoding block;

a third column decoding block configured to decode the n column addresses to activate at least one third column selection line of at least 2ⁿ third column selection lines, the at least one third column selection line corresponding to the column address decoded by the third column decoding block; and

a fourth column decoding block configured to decode the n column addresses to activate at least one fourth column selection line of at least 2ⁿ fourth column selection lines, the at least one fourth column selection line corresponding to the column address decoded by the fourth column decoding block.

4. A core section comprising:

a plurality of memory cell arrays having a first memory cell array, a second memory cell array, a third memory cell array and a fourth memory cell array;

a plurality of local data lines having a first local data line, a second local data line, a third local data line, and a fourth local data line, the first local data line being connected to or disconnected from the first memory cell array in response to a signal of a column selection line, the signal is related to a mode selection signal that represents a DDR1 mode operation or a DDR2 mode operation, the second local data line being connected to or disconnected from the second memory cell array in response to the signal, the third local data line being connected to or disconnected from the third memory cell array in response to the signal, the fourth local data line being connected to or disconnected from the fourth memory cell array in response to the signal; and

a plurality of global data lines having a first global data line corresponding to the first local data line, a second global data line corresponding to the second local data line, a third global data line corresponding to the third local data line, and a fourth global data line corresponding to the fourth local data line.

5. An input latch comprising:

a first prefetch circuit configured to prefetch at least one input data in response to an internal clock;

a second prefetch circuit configured to selectively prefetch an output of the first prefetch circuit in response to the mode selection signal; and

a prefetch control signal generator configured to control the second prefetch circuit in response to the mode selection signal.

6. An input ordering circuit comprising:

an ordering input generating circuit configured to select output data outputted from an input latch in response to the mode selection signal;

a control signal generating circuit configured to generate a control signal based on at least one column address and the mode selection signal; and

a data selecting circuit configured to select ordering input data generated from the ordering input generating circuit in response to the control signal to output the selected ordering input data.

7. An output ordering circuit comprising:

an output control signal generator configured to activate at least one of first, second, third and fourth control lines (FRT0, FRT1, FRT2 and FRT3) based on a mode selection signal and a least significant column address (CA0) and a most significant column address (CA1), the mode selection signal representing a DDR1 mode operation or a DDR2 mode operation;

a data sense amplifier configured to amplify data of a global data line; and

an output ordering control circuit configured to selectively output an output of the data sense amplifier to at least one of four output lines based on a control signal of the activated control line.

8. An output data latch/mux comprising:

an output data control signal generator configured to control a sampling of data outputted from an output ordering circuit in response to a mode selection signal or an internal clock, the mode selection signal representing a DDR1 mode operation or a DDR2 mode operation;

an output line selecting circuit configured to select one of output data lines based on a control signal that activates the output data latch/mux; and

a data transfer circuit configured to control a transmission of the data outputted from the output ordering circuit based on an output of the output data control signal generator.

9. An ODT (On Die Termination) circuit comprising:

a pad coupled to data pin, an address pin or a command pin;

at least one pull-up transistor, coupled between the pad and a first power voltage, configured to be turned on in response to a mode selection signal that represents a DDR1 mode operation or a DDR2 mode operation; and

at least one pull-down transistor, coupled between the pad and a second power voltage, configured to be turned on in response to the mode selection signal.

10. A dual data rate dynamic random access memory (DDR DRAM) device comprising:

a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.

11. A device according to claim 10 further comprising:

a column decoder configured to select two global data lines in the DDR1 mode responsive to a column address applied thereto and configured to select four global data lines in the DDR2 mode responsive to the column address applied thereto.

12. A device according to claim 10 further comprising:

a core section configured to send/receive data to/from the two selected global data lines in DDR1 mode and configured to send/receive data to/from the four selected global data lines in DDR2 mode.

13. A device according to claim 11 wherein the column decoder is configured to disregard one column address bit to enable two column select signals therefrom in DDR1 mode and is configured to disregard two column address bits to enable four column select signals therefrom in DDR2 mode.

14. A device according to claim 10 further comprising:

an input latch configured to prefetch two data bits in DDR1 mode and configured to prefetch four data bits in DDR2 mode.

15. A device according to claim 14 wherein the input latch comprises:

first and second serially coupled latches, wherein, if the DDR2 mode is active, the input latch receives first, second, third and fourth data, the third and fourth data are latched by the first latch to be provided to an output of the input latch and the first and second data are by first and second latch to be provided to the output of the input latch, and wherein, if the DDR1 mode is active, the input latch receives fifth and sixth data, the fifth and sixth data are latched by the first latch to be provided to the output of the input latch.

16. A device according to claim 15 wherein the input latch is configured to provide the prefetched two bits to the output of the latch on the same clock edge in DDR1 mode and configured to provide the prefetched four bits to the output of the latch on the same clock edge in DDR2 mode.

17. A device according to claim 11 further comprising:

an input ordering circuit configured to order prefetched two or four bits on outputs of the input ordering circuit based on values of the column address and the DDR1 and DDR2 mode.

18. A device according to claim 17 wherein the input ordering circuit is configured to reverse the order of the prefetched two bits in DDR1 mode based on the column address;

and

wherein the input ordering circuit is configured to reverse the order of the prefetched four bits in DDR2 mode based on the column address.

19. A device according to claim 18 further comprising:

a connector circuit configured to couple ordered data provided from the input ordering circuit to global data I/O lines based on the DDR mode.

20. A device according to claim 11 further comprising:

an output ordering circuit configured to order prefetched two or four bits output from the core section based on values of the column address and the DDR1 and DDR2 mode.

21. A device according to claim 20 wherein the output ordering circuit is configured to reverse the order of the prefetched two bits in DDR1 mode based on the column address;

and

wherein the input ordering circuit is configured to reverse the order of the prefetched four bits in DDR2 mode based on the column address.

22. A device according to claim 10 wherein the DDR1 mode or the DDR2 mode is selected via metal wiring, an MRS mode bit, and/or a fuse.

23. A method of operating a dual mode DDR DRAM device comprising:

operating in a DDR1 mode responsive to a first mode selection signal; and

operating in a DDR2 mode of operation responsive to a second mode selection signal.