Fabrication method of semiconductor integrated circuit device

• US 20050153465A1
• Filed: 12/16/2004
• Published: 07/14/2005
• Est. Priority Date: 12/22/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Wada, Yuji, Seito, Akira, Namba, Masaaki
• Granted Patent: US 7,306,957 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G01R 31/286 External aspects, e.g. related to chambers, contacting devices or handlers
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56016 Apparatus features
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.

Claims

1. A fabrication method of semiconductor integrated circuit devices, comprising the steps of:

(a) taking one test board whose testing has been completed out of a thermostatic bath while testing is underway on a plurality of semiconductor integrated circuit devices mounted in a plurality of test boards, placed therein;

(b) dislodging the semiconductor integrated circuit devices from the test board taken out;

(c) mounting a plurality of semiconductor integrated circuit devices to be tested in the test board with the semiconductor integrated circuit devices dislodged therefrom; and

(d) taking the test board mounted with the semiconductor integrated circuit devices into the thermostatic bath and putting the test board taken in to the test.

2. The fabrication method of semiconductor integrated circuit devices according to claim 1, comprising the steps of:

mounting a plurality of semiconductor integrated circuit devices to be newly tested in the test board while testing is underway on the semiconductor integrated circuit devices mounted in the test boards placed in the thermostatic bath; and

taking the test board mounted with the semiconductor integrated circuit devices to be newly tested into the thermostatic bath when the test board whose testing has been completed is taken out of the thermostatic bath, and putting the test board to the test.

3. The fabrication method of semiconductor integrated circuit devices according to claim 2,

wherein in the thermostatic bath, first slots and second slots are different from each other in temperature.

4. The fabrication method of semiconductor integrated circuit devices according to claim 1, comprising the steps of:

testing the semiconductor integrated circuit devices mounted in the test board in the thermostatic bath set to a first temperature; and

testing the semiconductor integrated circuit devices mounted in the test board in the thermostatic bath set to a second temperature after the completion of testing at the first temperature.

5. The fabrication method of semiconductor integrated circuit devices according to claim 4, comprising the steps of:

setting the thermostatic bath to the first temperature and testing the semiconductor integrated circuit devices; and

setting the thermostatic bath to the second temperature after the completion of testing at the first temperature and testing the semiconductor integrated circuit devices.

6. The fabrication method of semiconductor integrated circuit devices according to claim 5,

wherein testing on the semiconductor integrated circuit devices at the first temperature and testing on the semiconductor integrated circuit devices at the second temperature are carried out in different thermostatic baths.

7. The fabrication method of semiconductor integrated circuit devices according to claim 1, comprising the steps of:

mounting semiconductor integrated circuit devices in the test board by a handler; and

supplying test boards mounted with the semiconductor integrated circuit devices to the thermostatic bath of the inspection machine one by one by the handler; and

sorting out and putting in the cooled semiconductor integrated circuit devices based on the test result by the handler after the completion of test.

8. The fabrication method of semiconductor integrated circuit devices according to claim 7,

wherein semiconductor integrated circuit devices mounted in a first test board by the handler and semiconductor integrated circuit devices mounted in a second test board by the handler are different from each other in type.

9. The fabrication method of semiconductor integrated circuit devices according to claim 1,

wherein the semiconductor integrated circuit devices comprises SiP products wherein a plurality of semiconductor chips, such as logic and semiconductor memory, are encapsulated in one package.

10-12. -12. (canceled)