Method and structure to develop a test program for semiconductor integrated circuits

• US 20050154551A1
• Filed: 08/13/2004
• Published: 07/14/2005
• Est. Priority Date: 02/14/2003
• Status: Active Grant

• Current Assignee: Advantest America R&D Center, Inc. (Advantest Corporation)
• Original Assignee: Advantest Corporation
• Inventors: Adachi, Toshiaki, Pramanick, Ankan, Elston, Mark, Krishnaswamy, Ramachandran
• Granted Patent: US 7,197,417 B2
• Time in Patent Office: Days
• US Class Current: 702/119
• CPC Class Codes: G01R 31/3183 Generation of test inputs, e.g. test vectors, patterns or sequences
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
• CPC Class Codes: G01R 31/318314 Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages simulation software G01R31/318357; emulators G06F11/261
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.

Claims

1. A method for developing a test program for a semiconductor test system, the test system including at least one test module for applying at least one test to a device-under-test according to the test program, comprising:

describing a test plan file in a test program language (TPL), wherein the test plan file describes at least one test of the test program;

describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, wherein the test class file describes an implementation of the at least one test of the test program; and

generating the test program using the test plan file, the test class file and the pre-header file.

2. The method of claim 1, wherein the system program language is C/C++.

3. The method of claim 1, wherein generating the test program comprises:

compiling the test plan file by a TPL compiler to form a derived test plan file described in the SPL; and

compiling the pre-header file by the TPL compiler to form a header file described in the SPL.

4. The method of claim 3, wherein compiling the test plan file comprises:

translating the test plan file from the TPL to the SPL; and

validating the test plan file using the pre-header file.

5. The method of claim 3, wherein compiling the pre-header file comprises:

inserting in the header file parameters described in a parameters section of the pre-header file; and

inserting in the header file source code referenced in a template section of the pre-header file.

6. The method of claim 3, further comprising:

compiling the derived test plan file by a SPL compiler to form a test plan object file, wherein the test plan object file references the header file; and

compiling the test class file by the SPL compiler to form a test class object file, wherein the SPL compiler uses the header file to form the test class object file.

7. The method of claim 6, further comprising:

linking the test plan object file and the test class object file to form the test program, wherein the test program is executable by the semiconductor test system.

8. A pre-header for generating a test program for a semiconductor test system, the pre-header comprising:

a parameters section for specifying at least one attribute of the test program; and

a template section for inserting source code into a header file of the test program.

9. The pre-header of claim 8, wherein the at least one attribute of the test program relates to a pattern list and a test condition.

10. The pre-header of claim 9, wherein the pattern list comprises at least one of the following parameters:

cardinality;

trace level;

member name;

set function; and

parameter description.

11. The pre-header of claim 9, wherein the test condition comprises at least one of the following parameters:

cardinality;

trace level;

member name;

set function; and

parameter description.

12. The pre-header of claim 8, wherein the template section comprises:

class name;

import declarations;

parameter array types;

parameter attributes;

parameter functions; and

parameter function implementations.

13. The pre-header of claim 8, wherein the pre-header is used by a test program language (TPL) compiler to generate a header file, and wherein the header file is described in a system program language (SPL).

14. The pre-header of claim 13, wherein the header file is used by a SPL compiler to generate a test class object file, and wherein the header file is referenced by the SPL compiler to generate a test plan object file.

15. The pre-header of claim 8, wherein the pre-header is used to support user-defined tests in the test program.

16. A method for validating a test program for a semiconductor test system, the test system including at least one test module for applying at least one test to a device-under-test according to the test program, comprising:

describing a test plan file in a test program language (TPL), wherein the test plan file describes at least one test of the test program;

describing a pre-header file in the TPL; and

validating the test plan file using the pre-header file.

17. The method of claim 16, wherein the pre-header file comprises:

a parameters section for specifying at least one attribute of the test program; and

a template section for inserting source code into a header file of the test program.

18. The pre-header of claim 17, wherein the at least one attribute of the test program relates to pattern list and test condition.

19. The method of claim 16, wherein validating the test plan file comprises verifying semantics of the test plan file.

20. The method of claim 16, wherein validating the test plan file further comprises verifying test entity attributes of the test plan file.

21. The method of claim 16, wherein validating the test plan file further comprises verifying functional calls and their corresponding parameters of the test plan.

22. A semiconductor test system, comprising:

at least one test module for applying at least one test to a device-under-test;

a controller for receiving a test plan file, a test class file and a corresponding pre-header file of the test class file, wherein the test plan file describes the at least one test in a test program language (TPL), and wherein the test class file describes an implementation of the at least one test in a system program language (SPL);

means for compiling the test plan file and the pre-header file to form a derived test plan file and a header file respectively; and

means for generating a test program using the test class file, the derived test plan file, and the header file.

23. The semiconductor test system of claim 22, wherein the pre-header file comprising:

a parameters section for specifying at least one attribute of the test program; and

a template section for inserting source code into the header file of the test program.

24. The semiconductor test system of claim 23, wherein the at least one attribute of the test program relates to a pattern list and a test condition.

25. The semiconductor test system of claim 24, wherein the pattern list comprises at least one of the following parameters:

cardinality;

trace level;

member name;

set function; and

parameter description.

26. The semiconductor test system of claim 24, wherein the test condition comprises at least one of the following parameters:

cardinality;

trace level;

member name;

set function; and

parameter description.

27. The semiconductor test system of claim 23, wherein the template section comprises:

class name;

import declarations;

parameter array types;

parameter attributes;

parameter functions; and

parameter function implementations.

28. The semiconductor test system of claim 22, wherein the system program language is C/C++.

29. The semiconductor test system of claim 22, wherein means for compiling the test plan file comprise:

means for translating the test plan file from the TPL to the SPL; and

means for validating the test plan using the pre-header file.

30. The semiconductor test system of claim 22, wherein means for compiling the pre-header file comprise:

means for inserting in the header file parameters described in a parameters section of the pre-header file; and

means for inserting in the header file source code referenced in a template section of the pre-header file.

31. The semiconductor test system of claim 22, wherein means for generating the test program comprise:

means for compiling the derived test plan file to form a test plan object file, wherein the test plan object file references the header file; and

means for compiling the test class file to form a test class object file, wherein the the header file is used to form the test class object file.

32. The semiconductor test system of claim 31, further comprising:

means for linking the test plan object file and the test class object file to form the test program, wherein the test program is executable by the semiconductor test system.